Loading asoc/lahaina.c +31 −41 Original line number Diff line number Diff line // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved. * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved. */ #include <linux/clk.h> Loading Loading @@ -76,6 +76,8 @@ #define TDM_CHANNEL_MAX 8 #define MI2S_NUM_CHANNELS 2 #define MSM_LL_QOS_VALUE 300 /* time in us to ensure LPM doesn't go in C3/C4 */ #define ADSP_STATE_READY_TIMEOUT_MS 3000 Loading Loading @@ -2866,23 +2868,6 @@ static u32 get_mi2s_bits_per_sample(u32 bit_format) return bit_per_sample; } static void update_mi2s_clk_val(int dai_id, int stream) { u32 bit_per_sample = 0; if (stream == SNDRV_PCM_STREAM_PLAYBACK) { bit_per_sample = get_mi2s_bits_per_sample(mi2s_rx_cfg[dai_id].bit_format); mi2s_clk[dai_id].clk_freq_in_hz = mi2s_rx_cfg[dai_id].sample_rate * 2 * bit_per_sample; } else { bit_per_sample = get_mi2s_bits_per_sample(mi2s_tx_cfg[dai_id].bit_format); mi2s_clk[dai_id].clk_freq_in_hz = mi2s_tx_cfg[dai_id].sample_rate * 2 * bit_per_sample; } } static int msm_mi2s_set_sclk(struct snd_pcm_substream *substream, bool enable) { int ret = 0; Loading @@ -2898,12 +2883,6 @@ static int msm_mi2s_set_sclk(struct snd_pcm_substream *substream, bool enable) goto err; } if (enable) { update_mi2s_clk_val(index, substream->stream); dev_dbg(rtd->card->dev, "%s: clock rate %ul\n", __func__, mi2s_clk[index].clk_freq_in_hz); } mi2s_clk[index].enable = enable; ret = afe_set_lpass_clock_v2(port_id, &mi2s_clk[index]); Loading Loading @@ -5380,6 +5359,7 @@ static int msm_mi2s_snd_startup(struct snd_pcm_substream *substream) struct snd_soc_card *card = rtd->card; struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card); int sample_rate = 0; u32 bit_per_sample = 0; dev_dbg(rtd->card->dev, "%s: substream = %s stream = %d, dai name %s, dai ID %d\n", Loading @@ -5401,39 +5381,49 @@ static int msm_mi2s_snd_startup(struct snd_pcm_substream *substream) mutex_lock(&mi2s_intf_conf[index].lock); if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { sample_rate = mi2s_rx_cfg[index].sample_rate; bit_per_sample = get_mi2s_bits_per_sample(mi2s_rx_cfg[index].bit_format); } else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { sample_rate = mi2s_tx_cfg[index].sample_rate; bit_per_sample = get_mi2s_bits_per_sample(mi2s_tx_cfg[index].bit_format); } else { pr_err("%s: invalid stream %d\n", __func__, substream->stream); ret = -EINVAL; goto vote_err; } if (++mi2s_intf_conf[index].ref_cnt == 1) { if (IS_MSM_INTERFACE_MI2S(index) && IS_FRACTIONAL(sample_rate)) { if (pdata->lpass_audio_hw_vote == NULL) { dev_err(rtd->card->dev, "%s: Invalid lpass audio hw node\n", __func__); ret = -EINVAL; goto vote_err; goto clean_up; } if (pdata->core_audio_vote_count == 0) { ret = clk_prepare_enable(pdata->lpass_audio_hw_vote); if (ret < 0) { dev_err(rtd->card->dev, "%s: audio vote error\n", __func__); goto vote_err; goto clean_up; } } pdata->core_audio_vote_count++; mi2s_intf_conf[index].audio_core_vote = true; } if (++mi2s_intf_conf[index].ref_cnt == 1) { /* Check if msm needs to provide the clock to the interface */ if (!mi2s_intf_conf[index].msm_is_mi2s_master) { mi2s_clk[index].clk_id = mi2s_ebit_clk[index]; fmt = SND_SOC_DAIFMT_CBM_CFM; } mi2s_clk[index].clk_freq_in_hz = (sample_rate * MI2S_NUM_CHANNELS * bit_per_sample); dev_dbg(rtd->card->dev, "%s: clock rate %ul\n", __func__, mi2s_clk[index].clk_freq_in_hz); ret = msm_mi2s_set_sclk(substream, true); if (ret < 0) { dev_err(rtd->card->dev, Loading Loading @@ -5509,8 +5499,8 @@ static void msm_mi2s_snd_shutdown(struct snd_pcm_substream *substream) if (ret < 0) pr_err("%s:clock disable failed for MI2S (%d); ret=%d\n", __func__, index, ret); } mi2s_disable_audio_vote(substream); } mutex_unlock(&mi2s_intf_conf[index].lock); } Loading Loading
asoc/lahaina.c +31 −41 Original line number Diff line number Diff line // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved. * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved. */ #include <linux/clk.h> Loading Loading @@ -76,6 +76,8 @@ #define TDM_CHANNEL_MAX 8 #define MI2S_NUM_CHANNELS 2 #define MSM_LL_QOS_VALUE 300 /* time in us to ensure LPM doesn't go in C3/C4 */ #define ADSP_STATE_READY_TIMEOUT_MS 3000 Loading Loading @@ -2866,23 +2868,6 @@ static u32 get_mi2s_bits_per_sample(u32 bit_format) return bit_per_sample; } static void update_mi2s_clk_val(int dai_id, int stream) { u32 bit_per_sample = 0; if (stream == SNDRV_PCM_STREAM_PLAYBACK) { bit_per_sample = get_mi2s_bits_per_sample(mi2s_rx_cfg[dai_id].bit_format); mi2s_clk[dai_id].clk_freq_in_hz = mi2s_rx_cfg[dai_id].sample_rate * 2 * bit_per_sample; } else { bit_per_sample = get_mi2s_bits_per_sample(mi2s_tx_cfg[dai_id].bit_format); mi2s_clk[dai_id].clk_freq_in_hz = mi2s_tx_cfg[dai_id].sample_rate * 2 * bit_per_sample; } } static int msm_mi2s_set_sclk(struct snd_pcm_substream *substream, bool enable) { int ret = 0; Loading @@ -2898,12 +2883,6 @@ static int msm_mi2s_set_sclk(struct snd_pcm_substream *substream, bool enable) goto err; } if (enable) { update_mi2s_clk_val(index, substream->stream); dev_dbg(rtd->card->dev, "%s: clock rate %ul\n", __func__, mi2s_clk[index].clk_freq_in_hz); } mi2s_clk[index].enable = enable; ret = afe_set_lpass_clock_v2(port_id, &mi2s_clk[index]); Loading Loading @@ -5380,6 +5359,7 @@ static int msm_mi2s_snd_startup(struct snd_pcm_substream *substream) struct snd_soc_card *card = rtd->card; struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card); int sample_rate = 0; u32 bit_per_sample = 0; dev_dbg(rtd->card->dev, "%s: substream = %s stream = %d, dai name %s, dai ID %d\n", Loading @@ -5401,39 +5381,49 @@ static int msm_mi2s_snd_startup(struct snd_pcm_substream *substream) mutex_lock(&mi2s_intf_conf[index].lock); if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { sample_rate = mi2s_rx_cfg[index].sample_rate; bit_per_sample = get_mi2s_bits_per_sample(mi2s_rx_cfg[index].bit_format); } else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { sample_rate = mi2s_tx_cfg[index].sample_rate; bit_per_sample = get_mi2s_bits_per_sample(mi2s_tx_cfg[index].bit_format); } else { pr_err("%s: invalid stream %d\n", __func__, substream->stream); ret = -EINVAL; goto vote_err; } if (++mi2s_intf_conf[index].ref_cnt == 1) { if (IS_MSM_INTERFACE_MI2S(index) && IS_FRACTIONAL(sample_rate)) { if (pdata->lpass_audio_hw_vote == NULL) { dev_err(rtd->card->dev, "%s: Invalid lpass audio hw node\n", __func__); ret = -EINVAL; goto vote_err; goto clean_up; } if (pdata->core_audio_vote_count == 0) { ret = clk_prepare_enable(pdata->lpass_audio_hw_vote); if (ret < 0) { dev_err(rtd->card->dev, "%s: audio vote error\n", __func__); goto vote_err; goto clean_up; } } pdata->core_audio_vote_count++; mi2s_intf_conf[index].audio_core_vote = true; } if (++mi2s_intf_conf[index].ref_cnt == 1) { /* Check if msm needs to provide the clock to the interface */ if (!mi2s_intf_conf[index].msm_is_mi2s_master) { mi2s_clk[index].clk_id = mi2s_ebit_clk[index]; fmt = SND_SOC_DAIFMT_CBM_CFM; } mi2s_clk[index].clk_freq_in_hz = (sample_rate * MI2S_NUM_CHANNELS * bit_per_sample); dev_dbg(rtd->card->dev, "%s: clock rate %ul\n", __func__, mi2s_clk[index].clk_freq_in_hz); ret = msm_mi2s_set_sclk(substream, true); if (ret < 0) { dev_err(rtd->card->dev, Loading Loading @@ -5509,8 +5499,8 @@ static void msm_mi2s_snd_shutdown(struct snd_pcm_substream *substream) if (ret < 0) pr_err("%s:clock disable failed for MI2S (%d); ret=%d\n", __func__, index, ret); } mi2s_disable_audio_vote(substream); } mutex_unlock(&mi2s_intf_conf[index].lock); } Loading