Loading asoc/codecs/bolero/bolero-cdc-regmap.c +4 −0 Original line number Diff line number Diff line Loading @@ -854,6 +854,10 @@ static bool bolero_is_volatile_register(struct device *dev, case BOLERO_CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_LSB: case BOLERO_CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_MSB: case BOLERO_CDC_RX_EC_ASRC2_STATUS_FIFO: case BOLERO_CDC_RX_SIDETONE_IIR0_IIR_COEF_B1_CTL: case BOLERO_CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL: case BOLERO_CDC_RX_SIDETONE_IIR1_IIR_COEF_B1_CTL: case BOLERO_CDC_RX_SIDETONE_IIR1_IIR_COEF_B2_CTL: return true; } return false; Loading Loading
asoc/codecs/bolero/bolero-cdc-regmap.c +4 −0 Original line number Diff line number Diff line Loading @@ -854,6 +854,10 @@ static bool bolero_is_volatile_register(struct device *dev, case BOLERO_CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_LSB: case BOLERO_CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_MSB: case BOLERO_CDC_RX_EC_ASRC2_STATUS_FIFO: case BOLERO_CDC_RX_SIDETONE_IIR0_IIR_COEF_B1_CTL: case BOLERO_CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL: case BOLERO_CDC_RX_SIDETONE_IIR1_IIR_COEF_B1_CTL: case BOLERO_CDC_RX_SIDETONE_IIR1_IIR_COEF_B2_CTL: return true; } return false; Loading