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Commit 443d5e39 authored by Rodrigo Vivi's avatar Rodrigo Vivi
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drm/i915/icl: MBUS B credit change 



No functional change. But just a minor change to keep
up with Spec, since it has changed since commit c3cc39c5
("drm/i915/icl: program mbus during pipe enable")

The instructions previously said to program pipe's
B credit = 24 / number of pipes, which is 8 for ICL.
Now the spec gives us direct values independent of number
of pipes. Let's keep in sync.

Also just a reorder on fields to make easier to compare
against spec's sequence: A -> BW -> B.

Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Mahesh Kumar <mahesh1.kumar@intel.com>
Cc: Arthur J Runyan <arthur.j.runyan@intel.com>
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: default avatarMahesh Kumar <mahesh1.kumar@intel.com>
Reviewed-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181004151814.6054-1-rodrigo.vivi@intel.com
parent dfdaa566

drivers/gpu/drm/i915/intel_display.c

+3 −4
Original line number Diff line number Diff line
@@ -5694,10 +5694,9 @@ static void icl_pipe_mbus_enable(struct intel_crtc *crtc) 
	enum pipe pipe = crtc->pipe;

	uint32_t val;



	val = MBUS_DBOX_BW_CREDIT(1) | MBUS_DBOX_A_CREDIT(2);



	/* Program B credit equally to all pipes */

	val |= MBUS_DBOX_B_CREDIT(24 / INTEL_INFO(dev_priv)->num_pipes);

	val = MBUS_DBOX_A_CREDIT(2);

	val |= MBUS_DBOX_BW_CREDIT(1);

	val |= MBUS_DBOX_B_CREDIT(8);



	I915_WRITE(PIPE_MBUS_DBOX_CTL(pipe), val);

}