Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit c3cc39c5 authored by Mahesh Kumar's avatar Mahesh Kumar Committed by Paulo Zanoni
Browse files

drm/i915/icl: program mbus during pipe enable 



This patch program default values of MBus credit during pipe enable.

Changes Since V1:
 - Add WARN_ON (Paulo)
 - Remove TODO comment
 - Program 0 during pipe disable
 - Rebase
Changes since V2:
 - We don't need to do anything when disabling the pipe
Changes since V3 (from Paulo):
 - Remove WARN() that we'll never be able to trigger (Ville).

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: default avatarJames Ausmus <james.ausmus@intel.com>
Signed-off-by: default avatarMahesh Kumar <mahesh1.kumar@intel.com>
Signed-off-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180205172131.20255-1-paulo.r.zanoni@intel.com
parent 4cb4585e

drivers/gpu/drm/i915/intel_display.c

+17 −0
Original line number Diff line number Diff line
@@ -5418,6 +5418,20 @@ static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv, 
	I915_WRITE(CLKGATE_DIS_PSL(pipe), val);

}



static void icl_pipe_mbus_enable(struct intel_crtc *crtc)

{

	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

	enum pipe pipe = crtc->pipe;

	uint32_t val;



	val = MBUS_DBOX_BW_CREDIT(1) | MBUS_DBOX_A_CREDIT(2);



	/* Program B credit equally to all pipes */

	val |= MBUS_DBOX_B_CREDIT(24 / INTEL_INFO(dev_priv)->num_pipes);



	I915_WRITE(PIPE_MBUS_DBOX_CTL(pipe), val);

}



static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,

				struct drm_atomic_state *old_state)

{
@@ -5495,6 +5509,9 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config, 
	if (dev_priv->display.initial_watermarks != NULL)

		dev_priv->display.initial_watermarks(old_intel_state, pipe_config);



	if (INTEL_GEN(dev_priv) >= 11)

		icl_pipe_mbus_enable(intel_crtc);



	/* XXX: Do the pipe assertions at the right place for BXT DSI. */

	if (!transcoder_is_dsi(cpu_transcoder))

		intel_enable_pipe(pipe_config);