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Commit 439a6bb5 authored by Jerome Brunet's avatar Jerome Brunet Committed by Neil Armstrong
Browse files

clk: meson: ao-clkc: claim clock controller input clocks from DT 



Instead of relying on a fixed names for the differents input clocks
of the controller, get them through DT.

Signed-off-by: default avatarJerome Brunet <jbrunet@baylibre.com>
Reviewed-by: default avatarNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: default avatarNeil Armstrong <narmstrong@baylibre.com>
Link: https://lkml.kernel.org/r/20190116175435.4990-4-jbrunet@baylibre.com
parent 6e73dac7

drivers/clk/meson/axg-aoclk.c

+17 −5
Original line number Diff line number Diff line
@@ -16,6 +16,8 @@ 
#include "meson-aoclk.h"

#include "axg-aoclk.h"



#define IN_PREFIX "ao-in-"



/*

 * AO Configuration Clock registers offsets

 * Register offsets from the data sheet must be multiplied by 4.
@@ -38,7 +40,7 @@ static struct clk_regmap axg_aoclk_##_name = { \ 
	.hw.init = &(struct clk_init_data) {				\

		.name =  "axg_ao_" #_name,				\

		.ops = &clk_regmap_gate_ops,				\

		.parent_names = (const char *[]){ "clk81" },		\

		.parent_names = (const char *[]){ IN_PREFIX "mpeg-clk" }, \

		.num_parents = 1,					\

		.flags = CLK_IGNORE_UNUSED,				\

	},								\
@@ -60,7 +62,7 @@ static struct clk_regmap axg_aoclk_cts_oscin = { 
	.hw.init = &(struct clk_init_data){

		.name = "cts_oscin",

		.ops = &clk_regmap_gate_ro_ops,

		.parent_names = (const char *[]){ "xtal" },

		.parent_names = (const char *[]){ IN_PREFIX "xtal" },

		.num_parents = 1,

	},

};
@@ -167,7 +169,7 @@ static struct clk_regmap axg_aoclk_cts_rtc_oscin = { 
		.name = "axg_ao_cts_rtc_oscin",

		.ops = &clk_regmap_mux_ops,

		.parent_names = (const char *[]){ "axg_ao_32k",

						  "axg_ext_32k" },

						  IN_PREFIX "ext_32k-0" },

		.num_parents = 2,

		.flags = CLK_SET_RATE_PARENT,

	},
@@ -183,7 +185,7 @@ static struct clk_regmap axg_aoclk_clk81 = { 
	.hw.init = &(struct clk_init_data){

		.name = "axg_ao_clk81",

		.ops = &clk_regmap_mux_ro_ops,

		.parent_names = (const char *[]){ "clk81",

		.parent_names = (const char *[]){ IN_PREFIX "mpeg-clk",

						  "axg_ao_cts_rtc_oscin"},

		.num_parents = 2,

		.flags = CLK_SET_RATE_PARENT,
@@ -199,7 +201,8 @@ static struct clk_regmap axg_aoclk_saradc_mux = { 
	.hw.init = &(struct clk_init_data){

		.name = "axg_ao_saradc_mux",

		.ops = &clk_regmap_mux_ops,

		.parent_names = (const char *[]){ "xtal", "axg_ao_clk81" },

		.parent_names = (const char *[]){ IN_PREFIX "xtal",

						  "axg_ao_clk81" },

		.num_parents = 2,

	},

};
@@ -285,6 +288,12 @@ static const struct clk_hw_onecell_data axg_aoclk_onecell_data = { 
	.num = NR_CLKS,

};



static const struct meson_aoclk_input axg_aoclk_inputs[] = {

	{ .name = "xtal",	.required = true  },

	{ .name = "mpeg-clk",	.required = true  },

	{ .name = "ext-32k-0",	.required = false },

};



static const struct meson_aoclk_data axg_aoclkc_data = {

	.reset_reg	= AO_RTI_GEN_CNTL_REG0,

	.num_reset	= ARRAY_SIZE(axg_aoclk_reset),
@@ -292,6 +301,9 @@ static const struct meson_aoclk_data axg_aoclkc_data = { 
	.num_clks	= ARRAY_SIZE(axg_aoclk_regmap),

	.clks		= axg_aoclk_regmap,

	.hw_data	= &axg_aoclk_onecell_data,

	.inputs		= axg_aoclk_inputs,

	.num_inputs	= ARRAY_SIZE(axg_aoclk_inputs),

	.input_prefix	= IN_PREFIX,

};



static const struct of_device_id axg_aoclkc_match_table[] = {

drivers/clk/meson/gxbb-aoclk.c

+19 −6
Original line number Diff line number Diff line
@@ -9,6 +9,8 @@ 
#include "meson-aoclk.h"

#include "gxbb-aoclk.h"



#define IN_PREFIX "ao-in-"



/* AO Configuration Clock registers offsets */

#define AO_RTI_PWR_CNTL_REG1	0x0c

#define AO_RTI_PWR_CNTL_REG0	0x10
@@ -27,7 +29,7 @@ static struct clk_regmap _name##_ao = { \ 
	.hw.init = &(struct clk_init_data) {				\

		.name = #_name "_ao",					\

		.ops = &clk_regmap_gate_ops,				\

		.parent_names = (const char *[]){ "clk81" },		\

		.parent_names = (const char *[]){ IN_PREFIX "mpeg-clk" }, \

		.num_parents = 1,					\

		.flags = CLK_IGNORE_UNUSED,				\

	},								\
@@ -48,7 +50,7 @@ static struct clk_regmap ao_cts_oscin = { 
	.hw.init = &(struct clk_init_data){

		.name = "ao_cts_oscin",

		.ops = &clk_regmap_gate_ro_ops,

		.parent_names = (const char *[]){ "xtal" },

		.parent_names = (const char *[]){ IN_PREFIX "xtal" },

		.num_parents = 1,

	},

};
@@ -155,9 +157,9 @@ static struct clk_regmap ao_cts_rtc_oscin = { 
	.hw.init = &(struct clk_init_data){

		.name = "ao_cts_rtc_oscin",

		.ops = &clk_regmap_mux_ops,

		.parent_names = (const char *[]){ "ext_32k_0",

						  "ext_32k_1",

						  "ext_32k_2",

		.parent_names = (const char *[]){ IN_PREFIX "ext-32k-0",

						  IN_PREFIX "ext-32k-1",

						  IN_PREFIX "ext-32k-2",

						  "ao_32k" },

		.num_parents = 4,

		.flags = CLK_SET_RATE_PARENT,
@@ -174,7 +176,7 @@ static struct clk_regmap ao_clk81 = { 
	.hw.init = &(struct clk_init_data){

		.name = "ao_clk81",

		.ops = &clk_regmap_mux_ro_ops,

		.parent_names = (const char *[]){ "clk81",

		.parent_names = (const char *[]){ IN_PREFIX "mpeg-clk",

						  "ao_cts_rtc_oscin" },

		.num_parents = 2,

		.flags = CLK_SET_RATE_PARENT,
@@ -257,6 +259,14 @@ static const struct clk_hw_onecell_data gxbb_aoclk_onecell_data = { 
	.num = NR_CLKS,

};



static const struct meson_aoclk_input gxbb_aoclk_inputs[] = {

	{ .name = "xtal",	.required = true,  },

	{ .name = "mpeg-clk",	.required = true,  },

	{. name = "ext-32k-0",	.required = false, },

	{. name = "ext-32k-1",	.required = false, },

	{. name = "ext-32k-2",	.required = false, },

};



static const struct meson_aoclk_data gxbb_aoclkc_data = {

	.reset_reg	= AO_RTI_GEN_CNTL_REG0,

	.num_reset	= ARRAY_SIZE(gxbb_aoclk_reset),
@@ -264,6 +274,9 @@ static const struct meson_aoclk_data gxbb_aoclkc_data = { 
	.num_clks	= ARRAY_SIZE(gxbb_aoclk),

	.clks		= gxbb_aoclk,

	.hw_data	= &gxbb_aoclk_onecell_data,

	.inputs		= gxbb_aoclk_inputs,

	.num_inputs	= ARRAY_SIZE(gxbb_aoclk_inputs),

	.input_prefix	= IN_PREFIX,

};



static const struct of_device_id gxbb_aoclkc_match_table[] = {

drivers/clk/meson/meson-aoclk.c

+36 −1
Original line number Diff line number Diff line
@@ -14,7 +14,7 @@ 
#include <linux/reset-controller.h>

#include <linux/mfd/syscon.h>

#include <linux/of_device.h>

#include "clk-regmap.h"

#include <linux/slab.h>

#include "meson-aoclk.h"



static int meson_aoclk_do_reset(struct reset_controller_dev *rcdev,
@@ -31,6 +31,37 @@ static const struct reset_control_ops meson_aoclk_reset_ops = { 
	.reset = meson_aoclk_do_reset,

};



static int meson_aoclkc_register_inputs(struct device *dev,

					struct meson_aoclk_data *data)

{

	struct clk_hw *hw;

	char *str;

	int i;



	for (i = 0; i < data->num_inputs; i++) {

		const struct meson_aoclk_input *in = &data->inputs[i];



		str = kasprintf(GFP_KERNEL, "%s%s", data->input_prefix,

				in->name);

		if (!str)

			return -ENOMEM;



		hw = meson_clk_hw_register_input(dev, in->name, str, 0);

		kfree(str);



		if (IS_ERR(hw)) {

			if (!in->required && PTR_ERR(hw) == -ENOENT)

				continue;

			else if (PTR_ERR(hw) != -EPROBE_DEFER)

				dev_err(dev, "failed to register input %s\n",

					in->name);

			return PTR_ERR(hw);

		}

	}



	return 0;

}



int meson_aoclkc_probe(struct platform_device *pdev)

{

	struct meson_aoclk_reset_controller *rstc;
@@ -53,6 +84,10 @@ int meson_aoclkc_probe(struct platform_device *pdev) 
		return PTR_ERR(regmap);

	}



	ret = meson_aoclkc_register_inputs(dev, data);

	if (ret)

		return ret;



	/* Reset Controller */

	rstc->data = data;

	rstc->regmap = regmap;

drivers/clk/meson/meson-aoclk.h

+10 −2
Original line number Diff line number Diff line
@@ -13,14 +13,22 @@ 


#include <linux/platform_device.h>

#include <linux/reset-controller.h>

#include "clk-regmap.h"

#include "clkc.h"



struct meson_aoclk_input {

	const char *name;

	bool required;

};



struct meson_aoclk_data {

	const unsigned int			reset_reg;

	const int				num_reset;

	const unsigned int			*reset;

	int					num_clks;

	const int				num_clks;

	struct clk_regmap			**clks;

	const int				num_inputs;

	const struct meson_aoclk_input		*inputs;

	const char				*input_prefix;

	const struct clk_hw_onecell_data	*hw_data;

};