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Commit 6e73dac7 authored by Jerome Brunet's avatar Jerome Brunet Committed by Neil Armstrong
Browse files

clk: meson: axg: claim clock controller input clock from DT 



Instead of relying on a fixed name for the xtal clock, claim the
controller input clock trough DT.

Signed-off-by: default avatarJerome Brunet <jbrunet@baylibre.com>
Reviewed-by: default avatarNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: default avatarNeil Armstrong <narmstrong@baylibre.com>
Link: https://lkml.kernel.org/r/20190116175435.4990-3-jbrunet@baylibre.com
parent c0e6f5bf

drivers/clk/meson/axg.c

+19 −8
Original line number Diff line number Diff line
@@ -20,6 +20,8 @@ 
#include "clkc.h"

#include "axg.h"



#define IN_PREFIX "ee-in-"



static DEFINE_SPINLOCK(meson_clk_lock);



static struct clk_regmap axg_fixed_pll_dco = {
@@ -58,7 +60,7 @@ static struct clk_regmap axg_fixed_pll_dco = { 
	.hw.init = &(struct clk_init_data){

		.name = "fixed_pll_dco",

		.ops = &meson_clk_pll_ro_ops,

		.parent_names = (const char *[]){ "xtal" },

		.parent_names = (const char *[]){ IN_PREFIX "xtal" },

		.num_parents = 1,

	},

};
@@ -113,7 +115,7 @@ static struct clk_regmap axg_sys_pll_dco = { 
	.hw.init = &(struct clk_init_data){

		.name = "sys_pll_dco",

		.ops = &meson_clk_pll_ro_ops,

		.parent_names = (const char *[]){ "xtal" },

		.parent_names = (const char *[]){ IN_PREFIX "xtal" },

		.num_parents = 1,

	},

};
@@ -214,7 +216,7 @@ static struct clk_regmap axg_gp0_pll_dco = { 
	.hw.init = &(struct clk_init_data){

		.name = "gp0_pll_dco",

		.ops = &meson_clk_pll_ops,

		.parent_names = (const char *[]){ "xtal" },

		.parent_names = (const char *[]){ IN_PREFIX "xtal" },

		.num_parents = 1,

	},

};
@@ -283,7 +285,7 @@ static struct clk_regmap axg_hifi_pll_dco = { 
	.hw.init = &(struct clk_init_data){

		.name = "hifi_pll_dco",

		.ops = &meson_clk_pll_ops,

		.parent_names = (const char *[]){ "xtal" },

		.parent_names = (const char *[]){ IN_PREFIX "xtal" },

		.num_parents = 1,

	},

};
@@ -701,7 +703,7 @@ static struct clk_regmap axg_pcie_pll_dco = { 
	.hw.init = &(struct clk_init_data){

		.name = "pcie_pll_dco",

		.ops = &meson_clk_pll_ops,

		.parent_names = (const char *[]){ "xtal" },

		.parent_names = (const char *[]){ IN_PREFIX "xtal" },

		.num_parents = 1,

	},

};
@@ -803,7 +805,7 @@ static struct clk_regmap axg_pcie_cml_en1 = { 


static u32 mux_table_clk81[]	= { 0, 2, 3, 4, 5, 6, 7 };

static const char * const clk81_parent_names[] = {

	"xtal", "fclk_div7", "mpll1", "mpll2", "fclk_div4",

	IN_PREFIX "xtal", "fclk_div7", "mpll1", "mpll2", "fclk_div4",

	"fclk_div3", "fclk_div5"

};
@@ -852,7 +854,7 @@ static struct clk_regmap axg_clk81 = { 
};



static const char * const axg_sd_emmc_clk0_parent_names[] = {

	"xtal", "fclk_div2", "fclk_div3", "fclk_div5", "fclk_div7",

	IN_PREFIX "xtal", "fclk_div2", "fclk_div3", "fclk_div5", "fclk_div7",



	/*

	 * Following these parent clocks, we should also have had mpll2, mpll3
@@ -957,7 +959,7 @@ static struct clk_regmap axg_sd_emmc_c_clk0 = { 
static u32 mux_table_gen_clk[]	= { 0, 4, 5, 6, 7, 8,

				    9, 10, 11, 13, 14, };

static const char * const gen_clk_parent_names[] = {

	"xtal", "hifi_pll", "mpll0", "mpll1", "mpll2", "mpll3",

	IN_PREFIX "xtal", "hifi_pll", "mpll0", "mpll1", "mpll2", "mpll3",

	"fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7", "gp0_pll",

};
@@ -1263,6 +1265,7 @@ static const struct of_device_id clkc_match_table[] = { 
static int axg_clkc_probe(struct platform_device *pdev)

{

	struct device *dev = &pdev->dev;

	struct clk_hw *input;

	struct regmap *map;

	int ret, i;
@@ -1273,6 +1276,14 @@ static int axg_clkc_probe(struct platform_device *pdev) 
		return PTR_ERR(map);

	}



	input = meson_clk_hw_register_input(dev, "xtal", IN_PREFIX "xtal", 0);

	if (IS_ERR(input)) {

		ret = PTR_ERR(input);

		if (ret != -EPROBE_DEFER)

			dev_err(dev, "failed to get input clock");

		return ret;

	}



	/* Populate regmap for the regmap backed clocks */

	for (i = 0; i < ARRAY_SIZE(axg_clk_regmaps); i++)

		axg_clk_regmaps[i]->map = map;