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Commit 439297ec authored by Maxim Mikityanskiy's avatar Maxim Mikityanskiy Committed by Greg Kroah-Hartman
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net/mlx5e: Fix the value of MLX5E_MAX_RQ_NUM_MTTS 



[ Upstream commit 562696c3c62c7c23dd896e9447252ce9268cb812 ]

MLX5E_MAX_RQ_NUM_MTTS should be the maximum value, so that
MLX5_MTT_OCTW(MLX5E_MAX_RQ_NUM_MTTS) fits into u16. The current value of
1 << 17 results in MLX5_MTT_OCTW(1 << 17) = 1 << 16, which doesn't fit
into u16. This commit replaces it with the maximum value that still
fits u16.

Fixes: 73281b78 ("net/mlx5e: Derive Striding RQ size from MTU")
Signed-off-by: default avatarMaxim Mikityanskiy <maximmi@nvidia.com>
Reviewed-by: default avatarTariq Toukan <tariqt@nvidia.com>
Signed-off-by: default avatarSaeed Mahameed <saeedm@nvidia.com>
Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
parent 878e7f39

drivers/net/ethernet/mellanox/mlx5/core/en.h

+1 −1
Original line number Diff line number Diff line
@@ -101,7 +101,7 @@ struct page_pool; 
#define MLX5E_LOG_ALIGNED_MPWQE_PPW	(ilog2(MLX5E_REQUIRED_WQE_MTTS))

#define MLX5E_REQUIRED_MTTS(wqes)	(wqes * MLX5E_REQUIRED_WQE_MTTS)

#define MLX5E_MAX_RQ_NUM_MTTS	\

	((1 << 16) * 2) /* So that MLX5_MTT_OCTW(num_mtts) fits into u16 */

	(ALIGN_DOWN(U16_MAX, 4) * 2) /* So that MLX5_MTT_OCTW(num_mtts) fits into u16 */

#define MLX5E_ORDER2_MAX_PACKET_MTU (order_base_2(10 * 1024))

#define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW	\

		(ilog2(MLX5E_MAX_RQ_NUM_MTTS / MLX5E_REQUIRED_WQE_MTTS))