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Commit 42fa8c14 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
Browse files

Merge "ARM: dts: msm: Enable IO coherency with USB device on Shima"

parents 4001145d d1e625f0

qcom/shima-rumi.dtsi

+9 −0
Original line number Diff line number Diff line
@@ -45,7 +45,16 @@ 
	};

};



&usb2_phy0 {

	status = "disabled";

};



&usb_qmp_dp_phy {

	status = "disabled";

};



&usb0 {

	/delete-property/ extcon;

	dwc3@a600000 {

		usb-phy = <&usb_emu_phy_0>, <&usb_nop_phy>;

		maximum-speed = "high-speed";

qcom/shima-usb.dtsi

+238 −2
Original line number Diff line number Diff line 
#include <dt-bindings/clock/qcom,gcc-shima.h>

#include <dt-bindings/phy/qcom,shima-qmp-usb3.h>



&soc {

	usb0: ssusb@a600000 {
@@ -6,9 +7,14 @@ 
		reg = <0xa600000 0x100000>;

		reg-names = "core_base";



		iommus = <&apps_smmu 0xa0 0x0>;

		qcom,iommu-dma = "atomic";

		qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>;

		dma-coherent;

		#address-cells = <1>;

		#size-cells = <1>;

		ranges;

		dma-ranges;



		interrupts-extended = <&pdc 14 IRQ_TYPE_EDGE_RISING>,

			     <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
@@ -41,23 +47,253 @@ 
			0x144 /* GSI_RING_BASE_ADDR_H */

			0x1a4>; /* GSI_IF_STS */

		qcom,dwc-usb3-msm-tx-fifo-size = <27696>;

		extcon = <&eud>;



		interconnect-names = "usb-ddr", "usb-ipa", "ddr-usb";

		interconnects = <&aggre1_noc MASTER_USB3_0 &mc_virt SLAVE_EBI1>,

				<&aggre1_noc MASTER_USB3_0 &config_noc SLAVE_IPA_CFG>,

				<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_USB3_0>;



		dwc3@a600000 {

			compatible = "snps,dwc3";

			reg = <0xa600000 0xd93c>;

			interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;

			usb-phy = <&usb2_phy0>, <&usb_qmp_dp_phy>;

			linux,sysdev_is_parent;

			snps,disable-clk-gating;

			snps,has-lpm-erratum;

			snps,hird-threshold = /bits/ 8 <0x10>;

			snps,hird-threshold = /bits/ 8 <0x0>;

			snps,is-utmi-l1-suspend;

			snps,dis-u1-entry-quirk;

			snps,dis-u2-entry-quirk;

			snps,dis_u2_susphy_quirk;

			snps,dis_enblslpm_quirk;

			snps,ssp-u3-u0-quirk;

			tx-fifo-resize;

			maximum-speed = "super-speed-plus";

			dr_mode = "otg";

		};



	};



	/* Primary USB port related High Speed PHY */

	usb2_phy0: hsphy@88e3000 {

		compatible = "qcom,usb-hsphy-snps-femto";

		reg = <0x88e3000 0x114>,

			<0x088e2000 0x4>;

		reg-names = "hsusb_phy_base",

			"eud_enable_reg";



		vdd-supply = <&L10C>;

		vdda18-supply = <&L1C>;

		vdda33-supply = <&L2B>;

		qcom,vdd-voltage-level = <0 880000 880000>;



		clocks = <&rpmhcc RPMH_CXO_CLK>;

		clock-names = "ref_clk_src";



		resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;

		reset-names = "phy_reset";

		qcom,param-override-seq =

			<0x63 0x6c	/* override_x0 */

			 0xC8 0x70	/* override_x1 */

			 0x17 0x74>;	/* override x2 */

	};



	/* Primary USB port related QMP USB DP Combo PHY */

	usb_qmp_dp_phy: ssphy@88e8000 {

		compatible = "qcom,usb-ssphy-qmp-dp-combo";

		reg = <0x88e8000 0x3000>;

		reg-names = "qmp_phy_base";



		vdd-supply = <&L1B>;

		qcom,vdd-voltage-level = <0 912000 912000>;

		qcom,vdd-max-load-uA = <47000>;

		core-supply = <&L6B>;



		clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,

			<&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,

			<&gcc GCC_USB3_PRIM_PHY_PIPE_CLK_SRC>,

			<&usb3_phy_wrapper_gcc_usb30_pipe_clk>,

			<&rpmhcc RPMH_CXO_CLK>,

			<&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;

		clock-names = "aux_clk", "pipe_clk", "pipe_clk_mux",

				"pipe_clk_ext_src", "ref_clk_src",

				"com_aux_clk";



		resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,

			<&gcc GCC_USB3_PHY_PRIM_BCR>;

		reset-names = "global_phy_reset", "phy_reset";



		qcom,qmp-phy-reg-offset =

			<USB3_DP_PCS_PCS_STATUS1

			 USB3_DP_PCS_USB3_AUTONOMOUS_MODE_CTRL

			 USB3_DP_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR

			 USB3_DP_PCS_POWER_DOWN_CONTROL

			 USB3_DP_PCS_SW_RESET

			 USB3_DP_PCS_START_CONTROL

			 0xffff /* USB3_PHY_PCS_MISC_TYPEC_CTRL */

			 USB3_DP_COM_POWER_DOWN_CTRL

			 USB3_DP_COM_SW_RESET

			 USB3_DP_COM_RESET_OVRD_CTRL

			 USB3_DP_COM_PHY_MODE_CTRL

			 USB3_DP_COM_TYPEC_CTRL

			 USB3_DP_PCS_CLAMP_ENABLE>;



		qcom,qmp-phy-init-seq =

			/* <reg_offset, value, delay> */

			<USB3_DP_QSERDES_COM_SSC_EN_CENTER 0x01 0

			USB3_DP_QSERDES_COM_SSC_PER1 0x31 0

			USB3_DP_QSERDES_COM_SSC_PER2 0x01 0

			USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE0 0xDE 0

			USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE0 0x07 0

			USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE1 0xDE 0

			USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE1 0x07 0

			USB3_DP_QSERDES_COM_SYSCLK_BUF_ENABLE 0x0A 0

			USB3_DP_QSERDES_COM_CMN_IPTRIM 0x20 0

			USB3_DP_QSERDES_COM_CP_CTRL_MODE0 0x06 0

			USB3_DP_QSERDES_COM_CP_CTRL_MODE1 0x06 0

			USB3_DP_QSERDES_COM_PLL_RCTRL_MODE0 0x16 0

			USB3_DP_QSERDES_COM_PLL_RCTRL_MODE1 0x16 0

			USB3_DP_QSERDES_COM_PLL_CCTRL_MODE0 0x36 0

			USB3_DP_QSERDES_COM_PLL_CCTRL_MODE1 0x36 0

			USB3_DP_QSERDES_COM_SYSCLK_EN_SEL 0x1A 0

			USB3_DP_QSERDES_COM_LOCK_CMP_EN 0x04 0

			USB3_DP_QSERDES_COM_LOCK_CMP1_MODE0 0x14 0

			USB3_DP_QSERDES_COM_LOCK_CMP2_MODE0 0x34 0

			USB3_DP_QSERDES_COM_LOCK_CMP1_MODE1 0x34 0

			USB3_DP_QSERDES_COM_LOCK_CMP2_MODE1 0x82 0

			USB3_DP_QSERDES_COM_DEC_START_MODE0 0x82 0

			USB3_DP_QSERDES_COM_DEC_START_MODE1 0x82 0

			USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE0 0xAB 0

			USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE0 0xEA 0

			USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE0 0x02 0

			USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE1 0xAB 0

			USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE1 0xEA 0

			USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE1 0x02 0

			USB3_DP_QSERDES_COM_VCO_TUNE_MAP 0x02 0

			USB3_DP_QSERDES_COM_VCO_TUNE1_MODE0 0x24 0

			USB3_DP_QSERDES_COM_VCO_TUNE1_MODE1 0x24 0

			USB3_DP_QSERDES_COM_VCO_TUNE2_MODE1 0x02 0

			USB3_DP_QSERDES_COM_HSCLK_SEL 0x01 0

			USB3_DP_QSERDES_COM_CORECLK_DIV_MODE1 0x08 0

			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0xCA 0

			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1E 0

			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0xCA 0

			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1E 0

			USB3_DP_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL 0x11 0

			USB3_DP_QSERDES_TXA_RES_CODE_LANE_TX 0x00 0

			USB3_DP_QSERDES_TXA_RES_CODE_LANE_RX 0x00 0

			USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_TX 0x16 0

			USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_RX 0x0E 0

			USB3_DP_QSERDES_TXA_LANE_MODE_1 0x35 0

			USB3_DP_QSERDES_TXA_LANE_MODE_3 0x3F 0

			USB3_DP_QSERDES_TXA_LANE_MODE_4 0x7F 0

			USB3_DP_QSERDES_TXA_LANE_MODE_5 0x3F 0

			USB3_DP_QSERDES_TXA_RCV_DETECT_LVL_2 0x12 0

			USB3_DP_QSERDES_TXA_PI_QEC_CTRL 0x21 0

			USB3_DP_QSERDES_RXA_UCDR_FO_GAIN 0x0A 0

			USB3_DP_QSERDES_RXA_UCDR_SO_GAIN 0x05 0

			USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_FO_GAIN 0x2F 0

			USB3_DP_QSERDES_RXA_UCDR_SO_SATURATION_AND_ENABLE 0x7F 0

			USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_LOW 0xFF 0

			USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_HIGH 0x0F 0

			USB3_DP_QSERDES_RXA_UCDR_PI_CONTROLS 0x99 0

			USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH1 0x08 0

			USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH2 0x08 0

			USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN1 0x00 0

			USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN2 0x04 0

			USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL1 0x54 0

			USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL2 0x0F 0

			USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL2 0x0F 0

			USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL3 0x4A 0

			USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL4 0x0A 0

			USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_LOW 0xC0 0

			USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_HIGH 0x00 0

			USB3_DP_QSERDES_RXA_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x47 0

			USB3_DP_QSERDES_RXA_SIGDET_CNTRL 0x04 0

			USB3_DP_QSERDES_RXA_SIGDET_DEGLITCH_CNTRL 0x0E 0

			USB3_DP_QSERDES_RXA_RX_MODE_00_LOW 0xBB 0

			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH 0x7B 0

			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH2 0xBB 0

			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH3 0x3D 0

			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH4 0xDB 0

			USB3_DP_QSERDES_RXA_RX_MODE_01_LOW 0x64 0

			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH 0x24 0

			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH2 0xD2 0

			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH3 0x13 0

			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH4 0xA9 0

			USB3_DP_QSERDES_RXA_DFE_EN_TIMER 0x04 0

			USB3_DP_QSERDES_RXA_DFE_CTLE_POST_CAL_OFFSET 0x38 0

			USB3_DP_QSERDES_RXA_AUX_DATA_TCOARSE_TFINE 0xA0 0

			USB3_DP_QSERDES_RXA_DCC_CTRL1 0x0C 0

			USB3_DP_QSERDES_RXA_GM_CAL 0x00 0

			USB3_DP_QSERDES_RXA_VTH_CODE 0x10 0

			USB3_DP_QSERDES_TXB_RES_CODE_LANE_TX 0x00 0

			USB3_DP_QSERDES_TXB_RES_CODE_LANE_RX 0x00 0

			USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_TX 0x16 0

			USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_RX 0x0E 0

			USB3_DP_QSERDES_TXB_LANE_MODE_1 0x35 0

			USB3_DP_QSERDES_TXB_LANE_MODE_3 0x3F 0

			USB3_DP_QSERDES_TXB_LANE_MODE_4 0x7F 0

			USB3_DP_QSERDES_TXB_LANE_MODE_5 0x3F 0

			USB3_DP_QSERDES_TXB_RCV_DETECT_LVL_2 0x12 0

			USB3_DP_QSERDES_TXB_PI_QEC_CTRL 0x21 0

			USB3_DP_QSERDES_RXB_UCDR_SO_GAIN 0x05 0

			USB3_DP_QSERDES_RXB_UCDR_FO_GAIN 0x0A 0

			USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_FO_GAIN 0x2F 0

			USB3_DP_QSERDES_RXB_UCDR_SO_SATURATION_AND_ENABLE 0x7F 0

			USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_LOW 0xFF 0

			USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_HIGH 0x0F 0

			USB3_DP_QSERDES_RXB_UCDR_PI_CONTROLS 0x99 0

			USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH1 0x08 0

			USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH2 0x08 0

			USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN1 0x00 0

			USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN2 0x04 0

			USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL1 0x54 0

			USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL2 0x0F 0

			USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL2 0x0F 0

			USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL3 0x4A 0

			USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL4 0x0A 0

			USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_LOW 0xC0 0

			USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_HIGH 0x00 0

			USB3_DP_QSERDES_RXB_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x47 0

			USB3_DP_QSERDES_RXB_SIGDET_CNTRL 0x04 0

			USB3_DP_QSERDES_RXB_SIGDET_DEGLITCH_CNTRL 0x0E 0

			USB3_DP_QSERDES_RXB_RX_MODE_00_LOW 0xBB 0

			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH 0x7B 0

			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH2 0xBB 0

			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH3 0x3C 0

			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH4 0xDB 0

			USB3_DP_QSERDES_RXB_RX_MODE_01_LOW 0x64 0

			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH 0x24 0

			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH2 0xD2 0

			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH3 0x13 0

			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH4 0xA9 0

			USB3_DP_QSERDES_RXB_DFE_EN_TIMER 0x04 0

			USB3_DP_QSERDES_RXB_DFE_CTLE_POST_CAL_OFFSET 0x38 0

			USB3_DP_QSERDES_RXB_AUX_DATA_TCOARSE_TFINE 0xA0 0

			USB3_DP_QSERDES_RXB_DCC_CTRL1 0x0C 0

			USB3_DP_QSERDES_RXB_GM_CAL 0x00 0

			USB3_DP_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x40 0

			USB3_DP_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x00 0

			USB3_DP_PCS_RCVR_DTCT_DLY_P1U2_L 0xE7 0

			USB3_DP_PCS_RCVR_DTCT_DLY_P1U2_H 0x03 0

			USB3_DP_QSERDES_RXB_VTH_CODE 0x10 0

			USB3_DP_PCS_LOCK_DETECT_CONFIG1 0xD0 0

			USB3_DP_PCS_LOCK_DETECT_CONFIG2 0x07 0

			USB3_DP_PCS_LOCK_DETECT_CONFIG3 0x20 0

			USB3_DP_PCS_LOCK_DETECT_CONFIG6 0x13 0

			USB3_DP_PCS_REFGEN_REQ_CONFIG1 0x21 0

			USB3_DP_PCS_RX_SIGDET_LVL 0xAA 0

			USB3_DP_PCS_CDR_RESET_TIME 0x0A 0

			USB3_DP_PCS_ALIGN_DETECT_CONFIG1 0x88 0

			USB3_DP_PCS_ALIGN_DETECT_CONFIG2 0x13 0

			USB3_DP_PCS_PCS_TX_RX_CONFIG 0x0C 0

			USB3_DP_PCS_EQ_CONFIG1 0x4B 0

			USB3_DP_PCS_EQ_CONFIG5 0x10 0

			USB3_DP_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0xF8 0

			USB3_DP_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x07 0

			0xffffffff 0xffffffff 0x00>;

	};



	usb_nop_phy: usb_nop_phy {