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Commit 3fccda57 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "Revert "msm: kgsl: Add GPUCC register dumps to A6xx GPU snapshot""

parents f000bfd3 0dfdda9c

drivers/gpu/msm/a6xx_reg.h

+9 −0
Original line number Diff line number Diff line
@@ -543,6 +543,15 @@ 
#define A6XX_RBBM_CLOCK_MODE_HLSQ	 0x0011b

#define A6XX_RBBM_CLOCK_DELAY_HLSQ       0x0011c

#define A6XX_RBBM_CLOCK_HYST_HLSQ        0x0011d

#define A6XX_RBBM_CLOCK_CNTL_FCHE        0x00123

#define A6XX_RBBM_CLOCK_DELAY_FCHE       0x00124

#define A6XX_RBBM_CLOCK_HYST_FCHE        0x00125

#define A6XX_RBBM_CLOCK_CNTL_GLC         0x0012B

#define A6XX_RBBM_CLOCK_DELAY_GLC        0x00129

#define A6XX_RBBM_CLOCK_HYST_GLC         0x0012A

#define A6XX_RBBM_CLOCK_CNTL_MHUB        0x00126

#define A6XX_RBBM_CLOCK_DELAY_MHUB       0x00127

#define A6XX_RBBM_CLOCK_HYST_MHUB        0x00128



#define A6XX_GMUAO_GMU_CGC_MODE_CNTL     0x23b09

#define A6XX_GMUAO_GMU_CGC_DELAY_CNTL    0x23b0a

drivers/gpu/msm/adreno-gpulist.h

+83 −1
Original line number Diff line number Diff line
@@ -1223,7 +1223,7 @@ static const struct adreno_reglist a680_hwcg_regs[] = { 
	{A6XX_GMUGX_GMU_SP_RF_CONTROL_1, 0x00000001},

};



/* These apply to a640, a680, a612 and a610 */

/* These apply to a640, a680, a612, a610 and a702 */

static const struct adreno_reglist a640_vbif_regs[] = {

	{A6XX_GBIF_QSB_SIDE0, 0x00071620},

	{A6XX_GBIF_QSB_SIDE1, 0x00071620},
@@ -1745,6 +1745,87 @@ static const struct adreno_a6xx_core adreno_gpu_core_a635 = { 
	.ctxt_record_size = 2496 * 1024,

};



static const struct adreno_reglist a702_hwcg_regs[] = {

	{A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222},

	{A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},

	{A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000081},

	{A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},

	{A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222},

	{A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},

	{A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},

	{A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},

	{A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},

	{A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},

	{A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},

	{A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},

	{A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},

	{A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},

	{A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},

	{A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},

	{A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},

	{A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01202222},

	{A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},

	{A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},

	{A6XX_RBBM_CLOCK_CNTL_RAC, 0x05522022},

	{A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},

	{A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},

	{A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},

	{A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},

	{A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},

	{A6XX_RBBM_CLOCK_MODE_GPC, 0x02222222},

	{A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},

	{A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},

	{A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},

	{A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},

	{A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},

	{A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},

	{A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},

	{A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},

	{A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},

	{A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},

	{A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},

	{A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},

	{A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},

	{A6XX_RBBM_ISDB_CNT, 0x00000182},

	{A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},

	{A6XX_RBBM_SP_HYST_CNT, 0x00000000},

	{A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},

	{A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},

	{A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},

	{A6XX_RBBM_CLOCK_CNTL_FCHE, 0x00000222},

	{A6XX_RBBM_CLOCK_DELAY_FCHE, 0x00000000},

	{A6XX_RBBM_CLOCK_HYST_FCHE, 0x00000000},

	{A6XX_RBBM_CLOCK_CNTL_GLC, 0x00222222},

	{A6XX_RBBM_CLOCK_DELAY_GLC, 0x00000000},

	{A6XX_RBBM_CLOCK_HYST_GLC, 0x00000000},

	{A6XX_RBBM_CLOCK_CNTL_MHUB, 0x00000002},

	{A6XX_RBBM_CLOCK_DELAY_MHUB, 0x00000000},

	{A6XX_RBBM_CLOCK_HYST_MHUB, 0x00000000},

};



static const struct adreno_a6xx_core adreno_gpu_core_a702 = {

	.base = {

		DEFINE_ADRENO_REV(ADRENO_REV_A702, 7, 0, 2, ANY_ID),

		.features = ADRENO_CONTENT_PROTECTION |

					ADRENO_APRIV | ADRENO_PREEMPTION,

		.gpudev = &adreno_a6xx_gpudev,

		.perfcounters = &adreno_a6xx_legacy_perfcounters,

		.gmem_size = SZ_128K,

		.bus_width = 16,

		.snapshot_size = SZ_1M,

	},

	.prim_fifo_threshold = 0x0000c000,

	.sqefw_name = "a702_sqe.fw",

	.zap_name = "a702_zap",

	.hwcg = a702_hwcg_regs,

	.hwcg_count = ARRAY_SIZE(a702_hwcg_regs),

	.vbif = a640_vbif_regs,

	.vbif_count = ARRAY_SIZE(a640_vbif_regs),

	.hang_detect_cycles = 0x3ffff,

	.protected_regs = a620_protected_regs,

	.highest_bank_bit = 14,

};



static const struct adreno_gpu_core *adreno_gpulist[] = {

	&adreno_gpu_core_a306.base,

	&adreno_gpu_core_a306a.base,
@@ -1781,4 +1862,5 @@ static const struct adreno_gpu_core *adreno_gpulist[] = { 
	&adreno_gpu_core_a616.base,

	&adreno_gpu_core_a610.base,

	&adreno_gpu_core_a660_shima.base,

	&adreno_gpu_core_a702.base,

};

drivers/gpu/msm/adreno.h

+3 −1
Original line number Diff line number Diff line
@@ -205,6 +205,7 @@ enum adreno_gpurev { 
	ADRENO_REV_A650 = 650,

	ADRENO_REV_A660 = 660,

	ADRENO_REV_A680 = 680,

	ADRENO_REV_A702 = 702,

};



#define ADRENO_SOFT_FAULT BIT(0)
@@ -1049,7 +1050,7 @@ static inline int adreno_is_a505_or_a506(struct adreno_device *adreno_dev) 
static inline int adreno_is_a6xx(struct adreno_device *adreno_dev)

{

	return ADRENO_GPUREV(adreno_dev) >= 600 &&

			ADRENO_GPUREV(adreno_dev) < 700;

			ADRENO_GPUREV(adreno_dev) <= 702;

}



static inline int adreno_is_a660_shima(struct adreno_device *adreno_dev)
@@ -1070,6 +1071,7 @@ ADRENO_TARGET(a635, ADRENO_REV_A635) 
ADRENO_TARGET(a640, ADRENO_REV_A640)

ADRENO_TARGET(a650, ADRENO_REV_A650)

ADRENO_TARGET(a680, ADRENO_REV_A680)

ADRENO_TARGET(a702, ADRENO_REV_A702)



/* A635 is derived from A660 and shares same logic */

static inline int adreno_is_a660(struct adreno_device *adreno_dev)

drivers/gpu/msm/adreno_a6xx.c

+15 −4
Original line number Diff line number Diff line
@@ -231,6 +231,8 @@ __get_rbbm_clock_cntl_on(struct adreno_device *adreno_dev) 
		return 0x8AA8AA02;

	else if (adreno_is_a612(adreno_dev) || adreno_is_a610(adreno_dev))

		return 0xAAA8AA82;

	else if (adreno_is_a702(adreno_dev))

		return 0xAAAAAA82;

	else

		return 0x8AA8AA82;

}
@@ -373,7 +375,7 @@ static void a6xx_hwcg_set(struct adreno_device *adreno_dev, bool on) 
	 */



	if (gmu_core_isenabled(device) && !adreno_is_a612(adreno_dev) &&

		!adreno_is_a610(adreno_dev))

		!adreno_is_a610(adreno_dev) && !(adreno_is_a702(adreno_dev)))

		gmu_core_regrmw(device,

			A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 1, 0);

	else if (adreno_is_a619_holi(adreno_dev))
@@ -392,7 +394,7 @@ static void a6xx_hwcg_set(struct adreno_device *adreno_dev, bool on) 
	 * Hence skip GMU_GX registers for A612.

	 */

	if (gmu_core_isenabled(device) && !adreno_is_a612(adreno_dev) &&

		!adreno_is_a610(adreno_dev))

		!adreno_is_a610(adreno_dev) && !adreno_is_a702(adreno_dev))

		gmu_core_regrmw(device,

			A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 0, 1);

	else if (adreno_is_a619_holi(adreno_dev))
@@ -590,10 +592,12 @@ void a6xx_start(struct adreno_device *adreno_dev) 
	kgsl_regwrite(device, A6XX_UCHE_CACHE_WAYS, 0x4);



	/* ROQ sizes are twice as big on a640/a680 than on a630 */

	if (ADRENO_GPUREV(adreno_dev) >= ADRENO_REV_A635) {

	if ((ADRENO_GPUREV(adreno_dev) >= ADRENO_REV_A635) &&

		!adreno_is_a702(adreno_dev)) {

		kgsl_regwrite(device, A6XX_CP_ROQ_THRESHOLDS_2, 0x02000140);

		kgsl_regwrite(device, A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362C);

	} else if (adreno_is_a612(adreno_dev) || adreno_is_a610(adreno_dev)) {

	} else if (adreno_is_a612(adreno_dev) || adreno_is_a610(adreno_dev) ||

			adreno_is_a702(adreno_dev)) {

		kgsl_regwrite(device, A6XX_CP_ROQ_THRESHOLDS_2, 0x00800060);

		kgsl_regwrite(device, A6XX_CP_ROQ_THRESHOLDS_1, 0x40201b16);

	} else {
@@ -608,6 +612,9 @@ void a6xx_start(struct adreno_device *adreno_dev) 
		/* For A612 and A610 Mem pool size is reduced to 48 */

		kgsl_regwrite(device, A6XX_CP_MEM_POOL_SIZE, 48);

		kgsl_regwrite(device, A6XX_CP_MEM_POOL_DBG_ADDR, 47);

	} else if (adreno_is_a702(adreno_dev)) {

		kgsl_regwrite(device, A6XX_CP_MEM_POOL_SIZE, 64);

		kgsl_regwrite(device, A6XX_CP_MEM_POOL_DBG_ADDR, 63);

	} else {

		kgsl_regwrite(device, A6XX_CP_MEM_POOL_SIZE, 128);

	}
@@ -718,6 +725,10 @@ void a6xx_start(struct adreno_device *adreno_dev) 
	if (a6xx_core->disable_tseskip)

		kgsl_regrmw(device, A6XX_PC_DBG_ECO_CNTL, 0, (1 << 9));



	/* Set the bit in HLSQ Cluster for A702 */

	if (adreno_is_a702(adreno_dev))

		kgsl_regwrite(device, A6XX_CP_CHICKEN_DBG, (1 << 24));



	/* Enable the GMEM save/restore feature for preemption */

	if (adreno_is_preemption_enabled(adreno_dev))

		kgsl_regwrite(device, A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE,

drivers/gpu/msm/adreno_a6xx_snapshot.c

+1 −7
Original line number Diff line number Diff line
@@ -325,12 +325,6 @@ static const unsigned int a6xx_gmu_wrapper_registers[] = { 
	0x1f840, 0x1f840, 0x1f844, 0x1f845, 0x1f887, 0x1f889, 0x1f8d0, 0x1f8d0,

	/* GMU AO*/

	0x23b0C, 0x23b0E, 0x23b15, 0x23b15,

	/* GPU CC */

	0x24000, 0x24012, 0x24040, 0x24052, 0x24400, 0x24404, 0x24407, 0x2440B,

	0x24415, 0x2441C, 0x2441E, 0x2442D, 0x2443C, 0x2443D, 0x2443F, 0x24440,

	0x24442, 0x24449, 0x24458, 0x2445A, 0x24540, 0x2455E, 0x24800, 0x24802,

	0x24C00, 0x24C02, 0x25400, 0x25402, 0x25800, 0x25802, 0x25C00, 0x25C02,

	0x26000, 0x26002,

};



enum a6xx_debugbus_id {
@@ -1780,7 +1774,7 @@ void a6xx_snapshot(struct adreno_device *adreno_dev, 


		kgsl_snapshot_add_section(device, KGSL_SNAPSHOT_SECTION_REGS,

			snapshot, a6xx_snapshot_gmu_wrapper_registers, &r);

	} else if (!gmu_core_isenabled(device)) {

	} else if (adreno_is_a610(adreno_dev) || adreno_is_a702(adreno_dev)) {

		adreno_snapshot_registers(device, snapshot,

				a6xx_gmu_wrapper_registers,

				ARRAY_SIZE(a6xx_gmu_wrapper_registers) / 2);