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Commit 37538bd8 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "msm: kgsl: Add a6xx GMU performance counters"

parents ae1bc951 7e2a1b51

drivers/gpu/msm/a6xx_reg.h

+30 −0
Original line number Diff line number Diff line
@@ -983,6 +983,36 @@ 
#define A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_4_H	0x1F84D

#define A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_5_L	0x1F84E

#define A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_5_H	0x1F84F

#define A6XX_GMU_CX_GMU_POWER_COUNTER_GMUCLK_0_L 0x1F850

#define A6XX_GMU_CX_GMU_POWER_COUNTER_GMUCLK_0_H 0x1F851

#define A6XX_GMU_CX_GMU_POWER_COUNTER_GMUCLK_1_L 0x1F852

#define A6XX_GMU_CX_GMU_POWER_COUNTER_GMUCLK_1_H 0x1F853

#define A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_2	0x1F860

#define A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_6_L	0x1F870

#define A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_6_H	0x1F871

#define A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_7_L	0x1F872

#define A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_7_H	0x1F843

#define A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_8_L	0x1F874

#define A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_8_H	0x1F875

#define A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_9_L	0x1F876

#define A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_9_H	0x1F877

#define A6XX_GMU_CX_GMU_ALWAYS_ON_COUNTER_L	0x1F888

#define A6XX_GMU_CX_GMU_ALWAYS_ON_COUNTER_H	0x1F889

#define A6XX_GMU_CX_GMU_PERF_COUNTER_ENABLE	0x1F8A0

#define A6XX_GMU_CX_GMU_PERF_COUNTER_SELECT_0	0x1F8A1

#define A6XX_GMU_CX_GMU_PERF_COUNTER_SELECT_1	0x1F8A2

#define A6XX_GMU_CX_GMU_PERF_COUNTER_0_L	0x1F8A4

#define A6XX_GMU_CX_GMU_PERF_COUNTER_0_H	0x1F8A5

#define A6XX_GMU_CX_GMU_PERF_COUNTER_1_L	0x1F8A6

#define A6XX_GMU_CX_GMU_PERF_COUNTER_1_H	0x1F8A7

#define A6XX_GMU_CX_GMU_PERF_COUNTER_2_L	0x1F8A8

#define A6XX_GMU_CX_GMU_PERF_COUNTER_2_H	0x1F8A9

#define A6XX_GMU_CX_GMU_PERF_COUNTER_3_L	0x1F8AA

#define A6XX_GMU_CX_GMU_PERF_COUNTER_3_H	0x1F8AB

#define A6XX_GMU_CX_GMU_PERF_COUNTER_4_L	0x1F8AC

#define A6XX_GMU_CX_GMU_PERF_COUNTER_4_H	0x1F8AD

#define A6XX_GMU_CX_GMU_PERF_COUNTER_5_L	0x1F8AE

#define A6XX_GMU_CX_GMU_PERF_COUNTER_5_H	0x1F8AF

#define A6XX_GMU_PWR_COL_INTER_FRAME_CTRL	0x1F8C0

#define A6XX_GMU_PWR_COL_INTER_FRAME_HYST	0x1F8C1

#define A6XX_GMU_PWR_COL_SPTPRAC_HYST		0x1F8C2

drivers/gpu/msm/adreno-gpulist.h

+40 −2
Original line number Diff line number Diff line
@@ -26,6 +26,7 @@ static const struct adreno_a3xx_core adreno_gpu_core_a306 = { 
		DEFINE_ADRENO_REV(ADRENO_REV_A306, 3, 0, 6, 0),

		.features = ADRENO_SOFT_FAULT_DETECT,

		.gpudev = &adreno_a3xx_gpudev,

		.perfcounters = &adreno_a3xx_perfcounters,

		.gmem_base = 0,

		.gmem_size = SZ_128K,

		.bus_width = 0,
@@ -48,6 +49,7 @@ static const struct adreno_a3xx_core adreno_gpu_core_a306a = { 
		DEFINE_ADRENO_REV(ADRENO_REV_A306A, 3, 0, 6, 0x20),

		.features = ADRENO_SOFT_FAULT_DETECT,

		.gpudev = &adreno_a3xx_gpudev,

		.perfcounters = &adreno_a3xx_perfcounters,

		.gmem_base = 0,

		.gmem_size = SZ_128K,

		.bus_width = 16,
@@ -68,6 +70,7 @@ static const struct adreno_a3xx_core adreno_gpu_core_a304 = { 
		DEFINE_ADRENO_REV(ADRENO_REV_A304, 3, 0, 4, 0),

		.features = ADRENO_SOFT_FAULT_DETECT,

		.gpudev = &adreno_a3xx_gpudev,

		.perfcounters = &adreno_a3xx_perfcounters,

		.gmem_base = 0,

		.gmem_size = (SZ_64K + SZ_32K),

		.bus_width = 0,
@@ -192,6 +195,7 @@ static const struct adreno_a5xx_core adreno_gpu_core_a530v2 = { 
			ADRENO_PREEMPTION |

			ADRENO_CONTENT_PROTECTION,

		.gpudev = &adreno_a5xx_gpudev,

		.perfcounters = &adreno_a5xx_perfcounters,

		.gmem_base = 0x100000,

		.gmem_size = SZ_1M,

		.bus_width = 32,
@@ -218,6 +222,7 @@ static const struct adreno_a5xx_core adreno_gpu_core_a530v3 = { 
			ADRENO_PREEMPTION |

			ADRENO_CONTENT_PROTECTION,

		.gpudev = &adreno_a5xx_gpudev,

		.perfcounters = &adreno_a5xx_perfcounters,

		.gmem_base = 0x100000,

		.gmem_size = SZ_1M,

		.bus_width = 32,
@@ -284,6 +289,7 @@ static const struct adreno_a5xx_core adreno_gpu_core_a505 = { 
		DEFINE_ADRENO_REV(ADRENO_REV_A505, 5, 0, 5, ANY_ID),

		.features = ADRENO_PREEMPTION,

		.gpudev = &adreno_a5xx_gpudev,

		.perfcounters = &adreno_a5xx_perfcounters,

		.gmem_base = 0x100000,

		.gmem_size = (SZ_128K + SZ_8K),

		.bus_width = 16,
@@ -303,6 +309,7 @@ static const struct adreno_a5xx_core adreno_gpu_core_a506 = { 
		.features = ADRENO_PREEMPTION |

			ADRENO_CONTENT_PROTECTION | ADRENO_CPZ_RETENTION,

		.gpudev = &adreno_a5xx_gpudev,

		.perfcounters = &adreno_a5xx_perfcounters,

		.gmem_base = 0x100000,

		.gmem_size = (SZ_128K + SZ_8K),

		.bus_width = 16,
@@ -381,6 +388,7 @@ static const struct adreno_a5xx_core adreno_gpu_core_a510 = { 
	.base = {

		DEFINE_ADRENO_REV(ADRENO_REV_A510, 5, 1, 0, ANY_ID),

		.gpudev = &adreno_a5xx_gpudev,

		.perfcounters = &adreno_a5xx_perfcounters,

		.gmem_base = 0x100000,

		.gmem_size = SZ_256K,

		.bus_width = 16,
@@ -506,6 +514,7 @@ static const struct adreno_a5xx_core adreno_gpu_core_a540v2 = { 
			ADRENO_CONTENT_PROTECTION |

			ADRENO_GPMU | ADRENO_SPTP_PC,

		.gpudev = &adreno_a5xx_gpudev,

		.perfcounters = &adreno_a5xx_perfcounters,

		.gmem_base = 0x100000,

		.gmem_size = SZ_1M,

		.bus_width = 32,
@@ -589,6 +598,7 @@ static const struct adreno_a5xx_core adreno_gpu_core_a512 = { 
		.features = ADRENO_PREEMPTION |

			ADRENO_CONTENT_PROTECTION | ADRENO_CPZ_RETENTION,

		.gpudev = &adreno_a5xx_gpudev,

		.perfcounters = &adreno_a5xx_perfcounters,

		.gmem_base = 0x100000,

		.gmem_size = (SZ_256K + SZ_16K),

		.bus_width = 32,
@@ -608,6 +618,7 @@ static const struct adreno_a5xx_core adreno_gpu_core_a508 = { 
		.features = ADRENO_PREEMPTION |

			ADRENO_CONTENT_PROTECTION | ADRENO_CPZ_RETENTION,

		.gpudev = &adreno_a5xx_gpudev,

		.perfcounters = &adreno_a5xx_perfcounters,

		.gmem_base = 0x100000,

		.gmem_size = (SZ_128K + SZ_8K),

		.bus_width = 32,
@@ -783,6 +794,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a630v2 = { 
			ADRENO_GPMU | ADRENO_CONTENT_PROTECTION |

			ADRENO_IOCOHERENT | ADRENO_PREEMPTION,

		.gpudev = &adreno_a630_gpudev,

		.perfcounters = &adreno_a630_perfcounters,

		.gmem_base = 0x100000,

		.gmem_size = SZ_1M,

		.bus_width = 32,
@@ -882,6 +894,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a615 = { 
			ADRENO_GPMU | ADRENO_CONTENT_PROTECTION | ADRENO_IFPC |

			ADRENO_IOCOHERENT,

		.gpudev = &adreno_a630_gpudev,

		.perfcounters = &adreno_a6xx_legacy_perfcounters,

		.gmem_base = 0x100000,

		.gmem_size = SZ_512K,

		.bus_width = 32,
@@ -909,6 +922,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a618 = { 
			ADRENO_GPMU | ADRENO_CONTENT_PROTECTION | ADRENO_IFPC |

			ADRENO_IOCOHERENT,

		.gpudev = &adreno_a630_gpudev,

		.perfcounters = &adreno_a6xx_legacy_perfcounters,

		.gmem_base = 0x100000,

		.gmem_size = SZ_512K,

		.bus_width = 32,
@@ -936,6 +950,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a619 = { 
			ADRENO_GPMU | ADRENO_CONTENT_PROTECTION | ADRENO_IFPC |

			ADRENO_IOCOHERENT,

		.gpudev = &adreno_a630_gpudev,

		.perfcounters = &adreno_a6xx_legacy_perfcounters,

		.gmem_base = 0x100000,

		.gmem_size = SZ_512K,

		.bus_width = 32,
@@ -962,6 +977,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a619_variant = { 
		.compatible = "qcom,adreno-gpu-a619-holi",

		.features =  ADRENO_PREEMPTION | ADRENO_CONTENT_PROTECTION,

		.gpudev = &adreno_a619_holi_gpudev,

		.perfcounters = &adreno_a6xx_legacy_perfcounters,

		.gmem_base = 0x100000,

		.gmem_size = SZ_512K,

		.bus_width = 32,
@@ -1076,7 +1092,12 @@ static const struct a6xx_protected_regs a620_protected_regs[] = { 
	{ A6XX_CP_PROTECT_REG + 30, 0x0be20, 0x0d5ff, 1 },

	{ A6XX_CP_PROTECT_REG + 31, 0x0f000, 0x0fbff, 1 },

	{ A6XX_CP_PROTECT_REG + 32, 0x0fc00, 0x11bff, 0 },

	{ A6XX_CP_PROTECT_REG + 47, 0x11c00, 0x11c00, 1 },

	{ A6XX_CP_PROTECT_REG + 33, 0x18400, 0x1a3ff, 1 },

	{ A6XX_CP_PROTECT_REG + 34, 0x1a800, 0x1c7ff, 1 },

	{ A6XX_CP_PROTECT_REG + 35, 0x1f400, 0x1f843, 1 },

	{ A6XX_CP_PROTECT_REG + 36, 0x1f844, 0x1f8bf, 0 },

	{ A6XX_CP_PROTECT_REG + 37, 0x1f887, 0x1f8a2, 1 },

	{ A6XX_CP_PROTECT_REG + 47, 0x1f8c0, 0x1f8c0, 1 },

	{ 0 },

};
@@ -1088,6 +1109,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a620 = { 
			ADRENO_IFPC | ADRENO_PREEMPTION | ADRENO_ACD |

			ADRENO_APRIV,

		.gpudev = &adreno_a630_gpudev,

		.perfcounters = &adreno_a6xx_perfcounters,

		.gmem_base = 0,

		.gmem_size = SZ_512K,

		.bus_width = 32,
@@ -1178,6 +1200,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a640 = { 
			ADRENO_CONTENT_PROTECTION | ADRENO_IOCOHERENT |

			ADRENO_IFPC | ADRENO_PREEMPTION,

		.gpudev = &adreno_a6xx_gmu_gpudev,

		.perfcounters = &adreno_a6xx_legacy_perfcounters,

		.gmem_base = 0x100000,

		.gmem_size = SZ_1M, //Verified 1MB

		.bus_width = 32,
@@ -1258,6 +1281,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a650 = { 
			ADRENO_IOCOHERENT | ADRENO_CONTENT_PROTECTION |

			ADRENO_IFPC | ADRENO_APRIV,

		.gpudev = &adreno_a6xx_gmu_gpudev,

		.perfcounters = &adreno_a6xx_perfcounters,

		.gmem_base = 0,

		.gmem_size = SZ_1M + SZ_128K, /* verified 1152kB */

		.bus_width = 32,
@@ -1287,6 +1311,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a650v2 = { 
			ADRENO_IFPC | ADRENO_PREEMPTION | ADRENO_ACD |

			ADRENO_LM | ADRENO_APRIV,

		.gpudev = &adreno_a6xx_gmu_gpudev,

		.perfcounters = &adreno_a6xx_perfcounters,

		.gmem_base = 0,

		.gmem_size = SZ_1M + SZ_128K, /* verified 1152kB */

		.bus_width = 32,
@@ -1313,6 +1338,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a680 = { 
		DEFINE_ADRENO_REV(ADRENO_REV_A680, 6, 8, 0, ANY_ID),

		.features = ADRENO_RPMH | ADRENO_GPMU,

		.gpudev = &adreno_a6xx_gmu_gpudev,

		.perfcounters = &adreno_a6xx_legacy_perfcounters,

		.gmem_base = 0x100000,

		.gmem_size = SZ_2M,

		.bus_width = 32,
@@ -1390,6 +1416,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a612 = { 
			ADRENO_IOCOHERENT | ADRENO_PREEMPTION | ADRENO_GPMU |

			ADRENO_IFPC,

		.gpudev = &adreno_a6xx_rgmu_gpudev,

		.perfcounters = &adreno_a6xx_legacy_perfcounters,

		.gmem_base = 0x100000,

		.gmem_size = (SZ_128K + SZ_4K),

		.bus_width = 32,
@@ -1415,6 +1442,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a616 = { 
			ADRENO_GPMU | ADRENO_CONTENT_PROTECTION | ADRENO_IFPC |

			ADRENO_IOCOHERENT,

		.gpudev = &adreno_a630_gpudev,

		.perfcounters = &adreno_a6xx_legacy_perfcounters,

		.gmem_base = 0x100000,

		.gmem_size = SZ_512K,

		.bus_width = 32,
@@ -1441,6 +1469,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a610 = { 
		.features = ADRENO_CONTENT_PROTECTION |

			ADRENO_PREEMPTION,

		.gpudev = &adreno_a6xx_gpudev,

		.perfcounters = &adreno_a6xx_legacy_perfcounters,

		.gmem_base = 0x100000,

		.gmem_size = (SZ_128K + SZ_4K),

		.bus_width = 32,
@@ -1545,7 +1574,13 @@ static const struct a6xx_protected_regs a660_protected_regs[] = { 
	{ A6XX_CP_PROTECT_REG + 31, 0x0d000, 0x0d5ff, 1 },

	{ A6XX_CP_PROTECT_REG + 32, 0x0f000, 0x0fbff, 1 },

	{ A6XX_CP_PROTECT_REG + 33, 0x0fc00, 0x11bff, 0 },

	{ A6XX_CP_PROTECT_REG + 47, 0x11c00, 0x11c00, 1 },

	{ A6XX_CP_PROTECT_REG + 34, 0x18400, 0x1a3ff, 1 },

	{ A6XX_CP_PROTECT_REG + 35, 0x1a400, 0x1c3ff, 1 },

	{ A6XX_CP_PROTECT_REG + 36, 0x1f400, 0x1f843, 1 },

	{ A6XX_CP_PROTECT_REG + 37, 0x1f844, 0x1f8bf, 0 },

	{ A6XX_CP_PROTECT_REG + 38, 0x1f860, 0x1f860, 1 },

	{ A6XX_CP_PROTECT_REG + 39, 0x1f887, 0x1f8a2, 1 },

	{ A6XX_CP_PROTECT_REG + 47, 0x1f8c0, 0x1f8c0, 1 },

	{ 0 },

};
@@ -1556,6 +1591,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a660 = { 
				ADRENO_IOCOHERENT | ADRENO_CONTENT_PROTECTION |

				ADRENO_IFPC | ADRENO_PREEMPTION,

		.gpudev = &adreno_a6xx_gmu_gpudev,

		.perfcounters = &adreno_a6xx_perfcounters,

		.gmem_base = 0,

		.gmem_size = SZ_1M + SZ_512K,

		.bus_width = 32,
@@ -1588,6 +1624,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a660v2 = { 
				ADRENO_IFPC | ADRENO_PREEMPTION | ADRENO_ACD |

				ADRENO_BCL,

		.gpudev = &adreno_a6xx_gmu_gpudev,

		.perfcounters = &adreno_a6xx_perfcounters,

		.gmem_base = 0,

		.gmem_size = SZ_1M + SZ_512K,

		.bus_width = 32,
@@ -1620,6 +1657,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a660_shima = { 
				ADRENO_IOCOHERENT | ADRENO_CONTENT_PROTECTION |

				ADRENO_IFPC | ADRENO_PREEMPTION,

		.gpudev = &adreno_a6xx_gmu_gpudev,

		.perfcounters = &adreno_a6xx_perfcounters,

		.gmem_base = 0,

		.gmem_size = SZ_1M + SZ_512K,

		.bus_width = 32,

drivers/gpu/msm/adreno.h

+1 −2
Original line number Diff line number Diff line
@@ -392,6 +392,7 @@ struct adreno_gpu_core { 
	const char *compatible;

	unsigned long features;

	struct adreno_gpudev *gpudev;

	const struct adreno_perfcounters *perfcounters;

	unsigned long gmem_base;

	size_t gmem_size;

	u32 bus_width;
@@ -762,8 +763,6 @@ struct adreno_gpudev { 
	const struct adreno_ft_perf_counters *ft_perf_counters;

	unsigned int ft_perf_counters_count;



	struct adreno_perfcounters *perfcounters;



	struct adreno_coresight *coresight[2];



	unsigned int vbif_xin_halt_ctrl0_mask;

drivers/gpu/msm/adreno_a3xx.c

+0 −1
Original line number Diff line number Diff line
@@ -1236,7 +1236,6 @@ struct adreno_gpudev adreno_a3xx_gpudev = { 
	.reg_offsets = a3xx_register_offsets,

	.ft_perf_counters = a3xx_ft_perf_counters,

	.ft_perf_counters_count = ARRAY_SIZE(a3xx_ft_perf_counters),

	.perfcounters = &adreno_a3xx_perfcounters,

	.irq_handler = a3xx_irq_handler,

	.vbif_xin_halt_ctrl0_mask = A30X_VBIF_XIN_HALT_CTRL0_MASK,

	.probe = a3xx_probe,

drivers/gpu/msm/adreno_a3xx.h

+1 −1
Original line number Diff line number Diff line
@@ -44,6 +44,6 @@ unsigned int a3xx_irq_pending(struct adreno_device *adreno_dev); 
void a3xx_snapshot(struct adreno_device *adreno_dev,

		struct kgsl_snapshot *snapshot);



extern struct adreno_perfcounters adreno_a3xx_perfcounters;

extern const struct adreno_perfcounters adreno_a3xx_perfcounters;



#endif /*__A3XX_H */