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Commit 34ce3544 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
Browse files

Merge "msm: pcie: update suppressible clock info"

parents 6e0b4392 f339edaa

drivers/pci/controller/pci-msm.c

+9 −9
Original line number Diff line number Diff line
@@ -859,9 +859,9 @@ static struct msm_pcie_clk_info_t 
	{NULL, "pcie_0_smmu_clk", 0, false, false},

	{NULL, "pcie_0_slv_q2a_axi_clk", 0, false, false},

	{NULL, "pcie_0_sleep_clk", 0, false, false},

	{NULL, "pcie_phy_refgen_clk", 0, false, true},

	{NULL, "pcie_tbu_clk", 0, false, true},

	{NULL, "pcie_ddrss_sf_tbu_clk", 0, false, true},

	{NULL, "pcie_phy_refgen_clk", 0, false, false},

	{NULL, "pcie_tbu_clk", 0, false, false},

	{NULL, "pcie_ddrss_sf_tbu_clk", 0, false, false},

	{NULL, "pcie_aggre_noc_0_axi_clk", 0, false, false},

	{NULL, "pcie_aggre_noc_1_axi_clk", 0, false, false},

	{NULL, "pcie_phy_cfg_ahb_clk", 0, false, false},
@@ -879,9 +879,9 @@ static struct msm_pcie_clk_info_t 
	{NULL, "pcie_1_smmu_clk", 0, false, false},

	{NULL, "pcie_1_slv_q2a_axi_clk", 0, false, false},

	{NULL, "pcie_1_sleep_clk", 0, false, false},

	{NULL, "pcie_phy_refgen_clk", 0, false, true},

	{NULL, "pcie_tbu_clk", 0, false, true},

	{NULL, "pcie_ddrss_sf_tbu_clk", 0, false, true},

	{NULL, "pcie_phy_refgen_clk", 0, false, false},

	{NULL, "pcie_tbu_clk", 0, false, false},

	{NULL, "pcie_ddrss_sf_tbu_clk", 0, false, false},

	{NULL, "pcie_aggre_noc_0_axi_clk", 0, false, false},

	{NULL, "pcie_aggre_noc_1_axi_clk", 0, false, false},

	{NULL, "pcie_phy_cfg_ahb_clk", 0, false, false},
@@ -899,9 +899,9 @@ static struct msm_pcie_clk_info_t 
	{NULL, "pcie_2_smmu_clk", 0, false, false},

	{NULL, "pcie_2_slv_q2a_axi_clk", 0, false, false},

	{NULL, "pcie_2_sleep_clk", 0, false, false},

	{NULL, "pcie_phy_refgen_clk", 0, false, true},

	{NULL, "pcie_tbu_clk", 0, false, true},

	{NULL, "pcie_ddrss_sf_tbu_clk", 0, false, true},

	{NULL, "pcie_phy_refgen_clk", 0, false, false},

	{NULL, "pcie_tbu_clk", 0, false, false},

	{NULL, "pcie_ddrss_sf_tbu_clk", 0, false, false},

	{NULL, "pcie_aggre_noc_0_axi_clk", 0, false, false},

	{NULL, "pcie_aggre_noc_1_axi_clk", 0, false, false},

	{NULL, "pcie_phy_cfg_ahb_clk", 0, false, false},