Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit f339edaa authored by Tony Truong's avatar Tony Truong Committed by Gerrit - the friendly Code Review server
Browse files

msm: pcie: update suppressible clock info 



Update info for suppressible PCIe clocks on chipsets on msm-5.4
and forward.

Change-Id: Ifcde0fbb607b1937e859993199724e916771bd13
Signed-off-by: default avatarTony Truong <truong@codeaurora.org>
parent 5e6a4ba4

drivers/pci/controller/pci-msm.c

+9 −9
Original line number Diff line number Diff line
@@ -864,9 +864,9 @@ static struct msm_pcie_clk_info_t 
	{NULL, "pcie_0_smmu_clk", 0, false, false},

	{NULL, "pcie_0_slv_q2a_axi_clk", 0, false, false},

	{NULL, "pcie_0_sleep_clk", 0, false, false},

	{NULL, "pcie_phy_refgen_clk", 0, false, true},

	{NULL, "pcie_tbu_clk", 0, false, true},

	{NULL, "pcie_ddrss_sf_tbu_clk", 0, false, true},

	{NULL, "pcie_phy_refgen_clk", 0, false, false},

	{NULL, "pcie_tbu_clk", 0, false, false},

	{NULL, "pcie_ddrss_sf_tbu_clk", 0, false, false},

	{NULL, "pcie_aggre_noc_0_axi_clk", 0, false, false},

	{NULL, "pcie_aggre_noc_1_axi_clk", 0, false, false},

	{NULL, "pcie_phy_cfg_ahb_clk", 0, false, false},
@@ -884,9 +884,9 @@ static struct msm_pcie_clk_info_t 
	{NULL, "pcie_1_smmu_clk", 0, false, false},

	{NULL, "pcie_1_slv_q2a_axi_clk", 0, false, false},

	{NULL, "pcie_1_sleep_clk", 0, false, false},

	{NULL, "pcie_phy_refgen_clk", 0, false, true},

	{NULL, "pcie_tbu_clk", 0, false, true},

	{NULL, "pcie_ddrss_sf_tbu_clk", 0, false, true},

	{NULL, "pcie_phy_refgen_clk", 0, false, false},

	{NULL, "pcie_tbu_clk", 0, false, false},

	{NULL, "pcie_ddrss_sf_tbu_clk", 0, false, false},

	{NULL, "pcie_aggre_noc_0_axi_clk", 0, false, false},

	{NULL, "pcie_aggre_noc_1_axi_clk", 0, false, false},

	{NULL, "pcie_phy_cfg_ahb_clk", 0, false, false},
@@ -904,9 +904,9 @@ static struct msm_pcie_clk_info_t 
	{NULL, "pcie_2_smmu_clk", 0, false, false},

	{NULL, "pcie_2_slv_q2a_axi_clk", 0, false, false},

	{NULL, "pcie_2_sleep_clk", 0, false, false},

	{NULL, "pcie_phy_refgen_clk", 0, false, true},

	{NULL, "pcie_tbu_clk", 0, false, true},

	{NULL, "pcie_ddrss_sf_tbu_clk", 0, false, true},

	{NULL, "pcie_phy_refgen_clk", 0, false, false},

	{NULL, "pcie_tbu_clk", 0, false, false},

	{NULL, "pcie_ddrss_sf_tbu_clk", 0, false, false},

	{NULL, "pcie_aggre_noc_0_axi_clk", 0, false, false},

	{NULL, "pcie_aggre_noc_1_axi_clk", 0, false, false},

	{NULL, "pcie_phy_cfg_ahb_clk", 0, false, false},