UPSTREAM: scsi: ufs-mediatek: Fix unbalanced clock on/off

MediaTek UFS clocks are separated to two parts and controlled by different
modules: ufs-mediatek and phy-ufs-mediatek.

If both Auto-Hibern8 and clk-gating feature are enabled, mphy power control
is not balanced thus unbalanced control also happens to the clocks probed
by phy-ufs-mediatek module.

Fix this issue by:

 - Promise usage of phy_power_on/off balanced

 - Remove phy_power_on/off control in suspend/resume vops since both can be
   handled in setup_clock vops only

Link: https://lore.kernel.org/r/20200601104646.15436-5-stanley.chu@mediatek.com


Reviewed-by: Peter Wang <peter.wang@mediatek.com>
Signed-off-by: Stanley Chu <stanley.chu@mediatek.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>

Bug: 151050916
(cherry picked from commit 561e3a8726b2dd94ce75cad6c9cab211551f368a)
Change-Id: I9d304e895a07c5e672a6b29e9c8d23edaeaf8a08
Signed-off-by: Stanley Chu <stanley.chu@mediatek.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>