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Commit 32d0be01 authored by Atish Patra's avatar Atish Patra Committed by Thomas Gleixner
Browse files

clocksource/drivers/riscv: Fix clocksource mask 



For all riscv architectures (RV32, RV64 and RV128), the clocksource
is a 64 bit incrementing counter.

Fix the clock source mask accordingly.

Tested on both 64bit and 32 bit virt machine in QEMU.

Fixes: 62b01943 ("clocksource: new RISC-V SBI timer driver")
Signed-off-by: default avatarAtish Patra <atish.patra@wdc.com>
Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
Reviewed-by: default avatarAnup Patel <anup@brainfault.org>
Cc: Albert Ou <aou@eecs.berkeley.edu>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: linux-riscv@lists.infradead.org
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Anup Patel <Anup.Patel@wdc.com>
Cc: Damien Le Moal <Damien.LeMoal@wdc.com>
Cc: stable@vger.kernel.org
Link: https://lkml.kernel.org/r/20190322215411.19362-1-atish.patra@wdc.com
parent 9039de40

drivers/clocksource/timer-riscv.c

+2 −3
Original line number Diff line number Diff line
@@ -58,7 +58,7 @@ static u64 riscv_sched_clock(void) 
static DEFINE_PER_CPU(struct clocksource, riscv_clocksource) = {

	.name		= "riscv_clocksource",

	.rating		= 300,

	.mask		= CLOCKSOURCE_MASK(BITS_PER_LONG),

	.mask		= CLOCKSOURCE_MASK(64),

	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,

	.read		= riscv_clocksource_rdtime,

};
@@ -120,8 +120,7 @@ static int __init riscv_timer_init_dt(struct device_node *n) 
		return error;

	}



	sched_clock_register(riscv_sched_clock,

			BITS_PER_LONG, riscv_timebase);

	sched_clock_register(riscv_sched_clock, 64, riscv_timebase);



	error = cpuhp_setup_state(CPUHP_AP_RISCV_TIMER_STARTING,

			 "clockevents/riscv/timer:starting",