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Unverified Commit 62b01943 authored by Palmer Dabbelt's avatar Palmer Dabbelt Committed by Palmer Dabbelt
Browse files

clocksource: new RISC-V SBI timer driver 



The RISC-V ISA defines a per-hart real-time clock and timer, which is
present on all systems.  The clock is accessed via the 'rdtime'
pseudo-instruction (which reads a CSR), and the timer is set via an SBI
call.

Contains various improvements from Atish Patra <atish.patra@wdc.com>.

Signed-off-by: default avatarDmitriy Cherkasov <dmitriy@oss-tech.org>
Signed-off-by: default avatarPalmer Dabbelt <palmer@dabbelt.com>
[hch: remove dead code, add SPDX tags, used riscv_of_processor_hart(),
 minor cleanups, merged  hotplug cpu support and other improvements
 from Atish]
Signed-off-by: default avatarChristoph Hellwig <hch@lst.de>
Acked-by: default avatarThomas Gleixner <tglx@linutronix.de>
Reviewed-by: default avatarAtish Patra <atish.patra@wdc.com>
Signed-off-by: default avatarPalmer Dabbelt <palmer@sifive.com>
parent 6ea0f26a

arch/riscv/include/asm/smp.h

+0 −3
Original line number Diff line number Diff line
@@ -24,9 +24,6 @@ 


#ifdef CONFIG_SMP



/* SMP initialization hook for setup_arch */

void __init init_clockevent(void);



/* SMP initialization hook for setup_arch */

void __init setup_smp(void);

arch/riscv/kernel/irq.c

+3 −0
Original line number Diff line number Diff line
@@ -30,6 +30,9 @@ asmlinkage void __irq_entry do_IRQ(struct pt_regs *regs, unsigned long cause) 


	irq_enter();

	switch (cause & ~INTERRUPT_CAUSE_FLAG) {

	case INTERRUPT_CAUSE_TIMER:

		riscv_timer_interrupt();

		break;

#ifdef CONFIG_SMP

	case INTERRUPT_CAUSE_SOFTWARE:

		/*

arch/riscv/kernel/smpboot.c

+0 −1
Original line number Diff line number Diff line
@@ -104,7 +104,6 @@ asmlinkage void __init smp_callin(void) 
	current->active_mm = mm;



	trap_init();

	init_clockevent();

	notify_cpu_starting(smp_processor_id());

	set_cpu_online(smp_processor_id(), 1);

	local_flush_tlb_all();

arch/riscv/kernel/time.c

+1 −8
Original line number Diff line number Diff line
@@ -18,12 +18,6 @@ 


unsigned long riscv_timebase;



void __init init_clockevent(void)

{

	timer_probe();

	csr_set(sie, SIE_STIE);

}



void __init time_init(void)

{

	struct device_node *cpu;
@@ -35,6 +29,5 @@ void __init time_init(void) 
	riscv_timebase = prop;



	lpj_fine = riscv_timebase / HZ;



	init_clockevent();

	timer_probe();

}

drivers/clocksource/Kconfig

+11 −0
Original line number Diff line number Diff line
@@ -609,4 +609,15 @@ config ATCPIT100_TIMER 
	help

	  This option enables support for the Andestech ATCPIT100 timers.



config RISCV_TIMER

	bool "Timer for the RISC-V platform"

	depends on RISCV

	default y

	select TIMER_PROBE

	select TIMER_OF

	help

	  This enables the per-hart timer built into all RISC-V systems, which

	  is accessed via both the SBI and the rdcycle instruction.  This is

	  required for all RISC-V systems.



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