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Commit 2f5aaa3d authored by Joseph Lo's avatar Joseph Lo Committed by Stephen Warren
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ARM: tegra: set up the correct L2 data RAM latency for Cortex-A15



When there is a cluster power down cycle in suspend, we need to set up
the correct L2 RAM data RAM latency to make L2 cache work correctly. This
is only needed for cluster 0 and needs to be done in tegra_resume before
the cache is enabled.

Signed-off-by: default avatarJoseph Lo <josephl@nvidia.com>
Signed-off-by: default avatarStephen Warren <swarren@nvidia.com>
parent ac2527bf
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