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Commit 2f4ca92f authored by Isaac J. Manjarres's avatar Isaac J. Manjarres
Browse files

ARM: dts: msm: Add GDSC regulator references for Lahaina's SMMUs 

Add references for the GDSC regulators for the APPS and GFX SMMU
devices on Lahaina, to allow the HLOS to vote for these
regulators prior to accessing the respective register spaces.

Change-Id: I6ec4049cd0c17804c3de038f7a821e907d47d3a2
parent b86dcec1

qcom/msm-arm-smmu-lahaina.dtsi

+10 −0
Original line number Diff line number Diff line
@@ -13,6 +13,8 @@ 
		#size-cells = <1>;

		#address-cells = <1>;

		ranges;

		qcom,regulator-names = "vdd";

		vdd-supply = <&gpu_cc_cx_gdsc>;



		clocks = <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>,

			 <&clock_gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
@@ -193,6 +195,8 @@ 
				<0x15182210 0x8>;

			reg-names = "base", "status-reg";

			qcom,stream-id-range = <0x800 0x400>;

			qcom,regulator-names = "vdd";

			vdd-supply = <&gcc_hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc>;

			interconnects = <&mmss_noc MASTER_MDP0

					 &mc_virt SLAVE_EBI1>;

		};
@@ -203,6 +207,8 @@ 
				<0x15182218 0x8>;

			reg-names = "base", "status-reg";

			qcom,stream-id-range = <0xc00 0x400>;

			qcom,regulator-names = "vdd";

			vdd-supply = <&gcc_hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc>;

			interconnects = <&mmss_noc MASTER_MDP0

					 &mc_virt SLAVE_EBI1>;

		};
@@ -253,6 +259,8 @@ 
				<0x15182240 0x8>;

			reg-names = "base", "status-reg";

			qcom,stream-id-range = <0x2000 0x400>;

			qcom,regulator-names = "vdd";

			vdd-supply = <&gcc_hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc>;

			interconnects = <&mmss_noc MASTER_CAMNOC_SF

					 &mc_virt SLAVE_EBI1>;

		};
@@ -263,6 +271,8 @@ 
				<0x15182248 0x8>;

			reg-names = "base", "status-reg";

			qcom,stream-id-range = <0x2400 0x400>;

			qcom,regulator-names = "vdd";

			vdd-supply = <&gcc_hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc>;

			interconnects = <&mmss_noc MASTER_CAMNOC_SF

					 &mc_virt SLAVE_EBI1>;

		};