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Commit 2d4ed3a9 authored by Michal Wajdeczko's avatar Michal Wajdeczko Committed by Chris Wilson
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drm/i915/guc: New GuC scratch registers for Gen11 



Gen11 adds new set of scratch registers that can be used for MMIO
based Host-to-Guc communication. Due to limited number of these
registers it is expected that host will use them only for command
transport buffers (CTB) communication setup if one is available.

Bspec: 21044

Signed-off-by: default avatarMichal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: default avatarDaniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20190527183613.17076-10-michal.wajdeczko@intel.com
parent 4a1f9dc1

drivers/gpu/drm/i915/intel_guc.c

+9 −3
Original line number Diff line number Diff line
@@ -56,9 +56,15 @@ void intel_guc_init_send_regs(struct intel_guc *guc) 
	enum forcewake_domains fw_domains = 0;

	unsigned int i;



	if (HAS_GUC_CT(dev_priv) && INTEL_GEN(dev_priv) >= 11) {

		guc->send_regs.base =

				i915_mmio_reg_offset(GEN11_SOFT_SCRATCH(0));

		guc->send_regs.count = GEN11_SOFT_SCRATCH_COUNT;

	} else {

		guc->send_regs.base = i915_mmio_reg_offset(SOFT_SCRATCH(0));

		guc->send_regs.count = GUC_MAX_MMIO_MSG_LEN;

		BUILD_BUG_ON(GUC_MAX_MMIO_MSG_LEN > SOFT_SCRATCH_COUNT);

	}



	for (i = 0; i < guc->send_regs.count; i++) {

		fw_domains |= intel_uncore_forcewake_for_reg(&dev_priv->uncore,

drivers/gpu/drm/i915/intel_guc_reg.h

+3 −0
Original line number Diff line number Diff line
@@ -51,6 +51,9 @@ 
#define SOFT_SCRATCH(n)			_MMIO(0xc180 + (n) * 4)

#define SOFT_SCRATCH_COUNT		16



#define GEN11_SOFT_SCRATCH(n)		_MMIO(0x190240 + (n) * 4)

#define GEN11_SOFT_SCRATCH_COUNT	4



#define UOS_RSA_SCRATCH(i)		_MMIO(0xc200 + (i) * 4)

#define UOS_RSA_SCRATCH_COUNT		64