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Commit 2ce262f4 authored by Arun Kumar K's avatar Arun Kumar K Committed by Tomasz Figa
Browse files

clk: samsung: exynos5420: Add clock IDs needed by GPU 



Adds IDs for the clocks needed by the ARM Mali GPU
in exynos5420.

Signed-off-by: default avatarArun Kumar K <arun.kk@samsung.com>
Signed-off-by: default avatarTomasz Figa <t.figa@samsung.com>
parent a5b219b4

drivers/clk/samsung/clk-exynos5420.c

+2 −2
Original line number Diff line number Diff line
@@ -363,7 +363,7 @@ static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = { 
	MUX(0, "mout_aclk66_psgen", aclk66_peric_p, SRC_TOP5, 4, 1),

	MUX(0, "mout_user_aclk333_g2d", user_aclk333_g2d_p, SRC_TOP5, 8, 1),

	MUX(0, "mout_user_aclk266_g2d", user_aclk266_g2d_p, SRC_TOP5, 12, 1),

	MUX_A(0, "mout_user_aclk_g3d", user_aclk_g3d_p,

	MUX_A(CLK_MOUT_G3D, "mout_user_aclk_g3d", user_aclk_g3d_p,

			SRC_TOP5, 16, 1, "aclkg3d"),

	MUX(0, "mout_user_aclk300_jpeg", user_aclk300_jpeg_p,

			SRC_TOP5, 20, 1),
@@ -373,7 +373,7 @@ static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = { 
			SRC_TOP5, 28, 1),



	MUX(0, "sclk_mpll", mpll_p, SRC_TOP6, 0, 1),

	MUX(0, "sclk_vpll", vpll_p, SRC_TOP6, 4, 1),

	MUX(CLK_MOUT_VPLL, "sclk_vpll", vpll_p, SRC_TOP6, 4, 1),

	MUX(0, "sclk_spll", spll_p, SRC_TOP6, 8, 1),

	MUX(0, "sclk_ipll", ipll_p, SRC_TOP6, 12, 1),

	MUX(0, "sclk_rpll", rpll_p, SRC_TOP6, 16, 1),

include/dt-bindings/clock/exynos5420.h

+2 −0
Original line number Diff line number Diff line
@@ -178,6 +178,8 @@ 


/* mux clocks */

#define CLK_MOUT_HDMI		640

#define CLK_MOUT_G3D		641

#define CLK_MOUT_VPLL		642



/* divider clocks */

#define CLK_DOUT_PIXEL		768