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Commit a5b219b4 authored by Tomasz Stanislawski's avatar Tomasz Stanislawski Committed by Tomasz Figa
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clk: samsung: exynos4: export sclk_hdmiphy clock 



Export sclk_hdmiphy clock to be usable from DT.

Signed-off-by: default avatarTomasz Stanislawski <t.stanislaws@samsung.com>
Signed-off-by: default avatarTomasz Figa <t.figa@samsung.com>
parent 20b82ae2

drivers/clk/samsung/clk-exynos4.c

+1 −1
Original line number Diff line number Diff line
@@ -428,7 +428,7 @@ static struct samsung_fixed_rate_clock exynos4_fixed_rate_ext_clks[] __initdata 
/* fixed rate clocks generated inside the soc */

static struct samsung_fixed_rate_clock exynos4_fixed_rate_clks[] __initdata = {

	FRATE(0, "sclk_hdmi24m", NULL, CLK_IS_ROOT, 24000000),

	FRATE(0, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 27000000),

	FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 27000000),

	FRATE(0, "sclk_usbphy0", NULL, CLK_IS_ROOT, 48000000),

};

include/dt-bindings/clock/exynos4.h

+1 −0
Original line number Diff line number Diff line
@@ -33,6 +33,7 @@ 
#define CLK_MOUT_MPLL_USER_C	18 /* Exynos4x12 only */

#define CLK_MOUT_CORE		19

#define CLK_MOUT_APLL		20

#define CLK_SCLK_HDMIPHY	22



/* gate for special clocks (sclk) */

#define CLK_SCLK_FIMC0		128