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Commit 2bb25c17 authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Daniel Vetter
Browse files

drm/i915: Populate mem_freq in init_gt_powerwave() 



init_clock_gating() is too late to read out the mem_freq. We already
want to print out the GPU MHz numbers before it's called. Move the
mem_freq setup to init_gt_powersave().

v2: Also kill the CHV_CZ_CLOCK_FREQ_MODE_* defines

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarDeepak S <deepak.s@linux.intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent b9897127

drivers/gpu/drm/i915/i915_reg.h

+0 −6
Original line number Diff line number Diff line
@@ -5650,12 +5650,6 @@ enum punit_power_well { 
						 GEN6_PM_RP_DOWN_THRESHOLD | \

						 GEN6_PM_RP_DOWN_TIMEOUT)



#define CHV_CZ_CLOCK_FREQ_MODE_200			200

#define CHV_CZ_CLOCK_FREQ_MODE_267			267

#define CHV_CZ_CLOCK_FREQ_MODE_320			320

#define CHV_CZ_CLOCK_FREQ_MODE_333			333

#define CHV_CZ_CLOCK_FREQ_MODE_400			400



#define GEN7_GT_SCRATCH_BASE			0x4F100

#define GEN7_GT_SCRATCH_REG_NUM			8

drivers/gpu/drm/i915/intel_pm.c

+43 −47
Original line number Diff line number Diff line
@@ -4106,11 +4106,27 @@ static void valleyview_cleanup_pctx(struct drm_device *dev) 
static void valleyview_init_gt_powersave(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;

	u32 val;



	valleyview_setup_pctx(dev);



	mutex_lock(&dev_priv->rps.hw_lock);



	val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);

	switch ((val >> 6) & 3) {

	case 0:

	case 1:

		dev_priv->mem_freq = 800;

		break;

	case 2:

		dev_priv->mem_freq = 1066;

		break;

	case 3:

		dev_priv->mem_freq = 1333;

		break;

	}

	DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);



	dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);

	dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;

	DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
@@ -4145,11 +4161,38 @@ static void valleyview_init_gt_powersave(struct drm_device *dev) 
static void cherryview_init_gt_powersave(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;

	u32 val;



	cherryview_setup_pctx(dev);



	mutex_lock(&dev_priv->rps.hw_lock);



	val = vlv_punit_read(dev_priv, CCK_FUSE_REG);

	switch ((val >> 2) & 0x7) {

	case 0:

	case 1:

		dev_priv->rps.cz_freq = 200;

		dev_priv->mem_freq = 1600;

		break;

	case 2:

		dev_priv->rps.cz_freq = 267;

		dev_priv->mem_freq = 1600;

		break;

	case 3:

		dev_priv->rps.cz_freq = 333;

		dev_priv->mem_freq = 2000;

		break;

	case 4:

		dev_priv->rps.cz_freq = 320;

		dev_priv->mem_freq = 1600;

		break;

	case 5:

		dev_priv->rps.cz_freq = 400;

		dev_priv->mem_freq = 1600;

		break;

	}

	DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);



	dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);

	dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;

	DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
@@ -5726,24 +5769,6 @@ static void ivybridge_init_clock_gating(struct drm_device *dev) 
static void valleyview_init_clock_gating(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;

	u32 val;



	mutex_lock(&dev_priv->rps.hw_lock);

	val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);

	mutex_unlock(&dev_priv->rps.hw_lock);

	switch ((val >> 6) & 3) {

	case 0:

	case 1:

		dev_priv->mem_freq = 800;

		break;

	case 2:

		dev_priv->mem_freq = 1066;

		break;

	case 3:

		dev_priv->mem_freq = 1333;

		break;

	}

	DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);



	I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
@@ -5819,35 +5844,6 @@ static void valleyview_init_clock_gating(struct drm_device *dev) 
static void cherryview_init_clock_gating(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;

	u32 val;



	mutex_lock(&dev_priv->rps.hw_lock);

	val = vlv_punit_read(dev_priv, CCK_FUSE_REG);

	mutex_unlock(&dev_priv->rps.hw_lock);

	switch ((val >> 2) & 0x7) {

	case 0:

	case 1:

			dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_200;

			dev_priv->mem_freq = 1600;

			break;

	case 2:

			dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_267;

			dev_priv->mem_freq = 1600;

			break;

	case 3:

			dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_333;

			dev_priv->mem_freq = 2000;

			break;

	case 4:

			dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_320;

			dev_priv->mem_freq = 1600;

			break;

	case 5:

			dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_400;

			dev_priv->mem_freq = 1600;

			break;

	}

	DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);



	I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);