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Commit b9897127 authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Daniel Vetter
Browse files

drm/i915: s, fb->bits_per_pixel/8, pixel_size, in primary plane code 



Use the pixel_size we got from drm_format_plane_cpp() instead of
fb->bits_per_pixel/8 when computing the primary plane page/linear
offsets. Avoids a few divs and makes the code more future proof
against funky pixel formats where bits_per_pixel isn't well defined.
This is what we already did in the sprite code.

Note that the relevant sprite patch was

commit ca320ac4
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date:   Wed Dec 19 12:14:22 2012 +0000

    drm/i915: Use pixel size for computing linear offsets into a sprite

This change was required on sprites because they support yuv formats
which have fb->bits_per_pixel undefined.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
[danvet: Add Chris' software archeology as a note to the commit
message.]
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent c9ba6fad

drivers/gpu/drm/i915/intel_display.c

+4 −4
Original line number Diff line number Diff line
@@ -2466,12 +2466,12 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc, 
	if (IS_G4X(dev))

		dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;



	linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);

	linear_offset = y * fb->pitches[0] + x * pixel_size;



	if (INTEL_INFO(dev)->gen >= 4) {

		intel_crtc->dspaddr_offset =

			intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,

						       fb->bits_per_pixel / 8,

						       pixel_size,

						       fb->pitches[0]);

		linear_offset -= intel_crtc->dspaddr_offset;

	} else {
@@ -2574,10 +2574,10 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc, 
	if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))

		dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;



	linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);

	linear_offset = y * fb->pitches[0] + x * pixel_size;

	intel_crtc->dspaddr_offset =

		intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,

					       fb->bits_per_pixel / 8,

					       pixel_size,

					       fb->pitches[0]);

	linear_offset -= intel_crtc->dspaddr_offset;

	if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {