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Commit 29815168 authored by Boris Brezillon's avatar Boris Brezillon Committed by Miquel Raynal
Browse files

mtd: rawnand: Get rid of chip->bits_per_cell 



Now that we inherit from nand_device, we can use
nand_device->memorg.bits_per_cell instead of having our own field at
the nand_chip level.

Signed-off-by: default avatarBoris Brezillon <bbrezillon@kernel.org>
Signed-off-by: default avatarMiquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: default avatarFrieder Schrempf <frieder.schrempf@kontron.de>
parent 7beb37e5

drivers/mtd/nand/raw/nand_base.c

+0 −4
Original line number Diff line number Diff line
@@ -4457,7 +4457,6 @@ void nand_decode_ext_id(struct nand_chip *chip) 


	/* The 3rd id byte holds MLC / multichip data */

	memorg->bits_per_cell = nand_get_bits_per_cell(id_data[2]);

	chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]);

	/* The 4th id byte is the important one */

	extid = id_data[3];
@@ -4501,7 +4500,6 @@ static void nand_decode_id(struct nand_chip *chip, struct nand_flash_dev *type) 


	/* All legacy ID NAND are small-page, SLC */

	memorg->bits_per_cell = 1;

	chip->bits_per_cell = 1;

}



/*
@@ -4544,7 +4542,6 @@ static bool find_full_id_nand(struct nand_chip *chip, 
		mtd->oobsize = memorg->oobsize;



		memorg->bits_per_cell = nand_get_bits_per_cell(id_data[2]);

		chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]);

		chip->chipsize = (uint64_t)type->chipsize << 20;

		memorg->eraseblocks_per_lun =

			DIV_ROUND_DOWN_ULL((u64)type->chipsize << 20,
@@ -4584,7 +4581,6 @@ static void nand_manufacturer_detect(struct nand_chip *chip) 


		/* The 3rd id byte holds MLC / multichip data */

		memorg->bits_per_cell = nand_get_bits_per_cell(chip->id.data[2]);

		chip->bits_per_cell = nand_get_bits_per_cell(chip->id.data[2]);

		chip->manufacturer.desc->ops->detect(chip);

	} else {

		nand_decode_ext_id(chip);

drivers/mtd/nand/raw/nand_hynix.c

+1 −1
Original line number Diff line number Diff line
@@ -592,7 +592,7 @@ static void hynix_nand_extract_scrambling_requirements(struct nand_chip *chip, 
	u8 nand_tech;



	/* We need scrambling on all TLC NANDs*/

	if (chip->bits_per_cell > 2)

	if (nanddev_bits_per_cell(&chip->base) > 2)

		chip->options |= NAND_NEED_SCRAMBLING;



	/* And on MLC NANDs with sub-3xnm process */

drivers/mtd/nand/raw/nand_jedec.c

+0 −1
Original line number Diff line number Diff line
@@ -104,7 +104,6 @@ int nand_jedec_detect(struct nand_chip *chip) 
	chip->chipsize = memorg->eraseblocks_per_lun;

	chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;

	memorg->bits_per_cell = p->bits_per_cell;

	chip->bits_per_cell = p->bits_per_cell;



	if (le16_to_cpu(p->features) & JEDEC_FEATURE_16_BIT_BUS)

		chip->options |= NAND_BUSWIDTH_16;

drivers/mtd/nand/raw/nand_micron.c

+1 −1
Original line number Diff line number Diff line
@@ -385,7 +385,7 @@ static int micron_supports_on_die_ecc(struct nand_chip *chip) 
	if (!chip->parameters.onfi)

		return MICRON_ON_DIE_UNSUPPORTED;



	if (chip->bits_per_cell != 1)

	if (nanddev_bits_per_cell(&chip->base) != 1)

		return MICRON_ON_DIE_UNSUPPORTED;



	/*

drivers/mtd/nand/raw/nand_onfi.c

+0 −1
Original line number Diff line number Diff line
@@ -249,7 +249,6 @@ int nand_onfi_detect(struct nand_chip *chip) 
	chip->chipsize = memorg->eraseblocks_per_lun;

	chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;

	memorg->bits_per_cell = p->bits_per_cell;

	chip->bits_per_cell = p->bits_per_cell;



	if (le16_to_cpu(p->features) & ONFI_FEATURE_16_BIT_BUS)

		chip->options |= NAND_BUSWIDTH_16;