Loading arch/mips/mm/c-r4k.c +1 −1 Original line number Original line Diff line number Diff line Loading @@ -862,7 +862,7 @@ static void __init probe_pcache(void) break; break; case CPU_VR4133: case CPU_VR4133: write_c0_config(config & ~CONF_EB); write_c0_config(config & ~VR41_CONF_P4K); case CPU_VR4131: case CPU_VR4131: /* Workaround for cache instruction bug of VR4131 */ /* Workaround for cache instruction bug of VR4131 */ if (c->processor_id == 0x0c80U || c->processor_id == 0x0c81U || if (c->processor_id == 0x0c80U || c->processor_id == 0x0c81U || Loading include/asm-mips/mipsregs.h +1 −0 Original line number Original line Diff line number Diff line Loading @@ -470,6 +470,7 @@ /* Bits specific to the VR41xx. */ /* Bits specific to the VR41xx. */ #define VR41_CONF_CS (_ULCAST_(1) << 12) #define VR41_CONF_CS (_ULCAST_(1) << 12) #define VR41_CONF_P4K (_ULCAST_(1) << 13) #define VR41_CONF_BP (_ULCAST_(1) << 16) #define VR41_CONF_BP (_ULCAST_(1) << 16) #define VR41_CONF_M16 (_ULCAST_(1) << 20) #define VR41_CONF_M16 (_ULCAST_(1) << 20) #define VR41_CONF_AD (_ULCAST_(1) << 23) #define VR41_CONF_AD (_ULCAST_(1) << 23) Loading Loading
arch/mips/mm/c-r4k.c +1 −1 Original line number Original line Diff line number Diff line Loading @@ -862,7 +862,7 @@ static void __init probe_pcache(void) break; break; case CPU_VR4133: case CPU_VR4133: write_c0_config(config & ~CONF_EB); write_c0_config(config & ~VR41_CONF_P4K); case CPU_VR4131: case CPU_VR4131: /* Workaround for cache instruction bug of VR4131 */ /* Workaround for cache instruction bug of VR4131 */ if (c->processor_id == 0x0c80U || c->processor_id == 0x0c81U || if (c->processor_id == 0x0c80U || c->processor_id == 0x0c81U || Loading
include/asm-mips/mipsregs.h +1 −0 Original line number Original line Diff line number Diff line Loading @@ -470,6 +470,7 @@ /* Bits specific to the VR41xx. */ /* Bits specific to the VR41xx. */ #define VR41_CONF_CS (_ULCAST_(1) << 12) #define VR41_CONF_CS (_ULCAST_(1) << 12) #define VR41_CONF_P4K (_ULCAST_(1) << 13) #define VR41_CONF_BP (_ULCAST_(1) << 16) #define VR41_CONF_BP (_ULCAST_(1) << 16) #define VR41_CONF_M16 (_ULCAST_(1) << 20) #define VR41_CONF_M16 (_ULCAST_(1) << 20) #define VR41_CONF_AD (_ULCAST_(1) << 23) #define VR41_CONF_AD (_ULCAST_(1) << 23) Loading