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Commit 26b09f18 authored by Greg Kroah-Hartman's avatar Greg Kroah-Hartman
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Merge 5.4.161 into android11-5.4-lts 



Changes in 5.4.161
	soc/tegra: pmc: Fix imbalanced clock disabling in error code path
	scsi: ufs: Fix interrupt error message for shared interrupts
	MIPS: Fix assembly error from MIPSr2 code used within MIPS_ISA_ARCH_LEVEL
	ext4: fix lazy initialization next schedule time computation in more granular unit
	scsi: ufs: Fix tm request when non-fatal error happens
	fortify: Explicitly disable Clang support
	parisc/entry: fix trace test in syscall exit path
	PCI/MSI: Destroy sysfs before freeing entries
	PCI/MSI: Deal with devices lying about their MSI mask capability
	PCI: Add MSI masking quirk for Nvidia ION AHCI
	erofs: remove the occupied parameter from z_erofs_pagevec_enqueue()
	erofs: fix unsafe pagevec reuse of hooked pclusters
	Linux 5.4.161

Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@google.com>
Change-Id: I5c1942d0f5c822a788147c7ade349701a9451cee
parents ebd1ef6e 5c088fba

Makefile

+1 −1
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0

VERSION = 5

PATCHLEVEL = 4

SUBLEVEL = 160

SUBLEVEL = 161

EXTRAVERSION =

NAME = Kleptomaniac Octopus

arch/mips/include/asm/cmpxchg.h

+3 −0
Original line number Diff line number Diff line
@@ -239,6 +239,7 @@ static inline unsigned long __cmpxchg64(volatile void *ptr, 
	"	.set	" MIPS_ISA_ARCH_LEVEL "		\n"

	/* Load 64 bits from ptr */

	"1:	lld	%L0, %3		# __cmpxchg64	\n"

	"	.set	pop				\n"

	/*

	 * Split the 64 bit value we loaded into the 2 registers that hold the

	 * ret variable.
@@ -266,6 +267,8 @@ static inline unsigned long __cmpxchg64(volatile void *ptr, 
	"	or	%L1, %L1, $at			\n"

	"	.set	at				\n"

#  endif

	"	.set	push				\n"

	"	.set	" MIPS_ISA_ARCH_LEVEL "		\n"

	/* Attempt to store new at ptr */

	"	scd	%L1, %2				\n"

	/* If we failed, loop! */

arch/parisc/kernel/entry.S

+1 −1
Original line number Diff line number Diff line
@@ -1842,7 +1842,7 @@ syscall_restore: 


	/* Are we being ptraced? */

	LDREG	TI_FLAGS-THREAD_SZ_ALGN-FRAME_SIZE(%r30),%r19

	ldi	_TIF_SYSCALL_TRACE_MASK,%r2

	ldi	_TIF_SINGLESTEP|_TIF_BLOCKSTEP,%r2

	and,COND(=)	%r19,%r2,%r0

	b,n	syscall_restore_rfi

drivers/pci/msi.c

+15 −12
Original line number Diff line number Diff line
@@ -394,18 +394,6 @@ static void free_msi_irqs(struct pci_dev *dev) 
			for (i = 0; i < entry->nvec_used; i++)

				BUG_ON(irq_has_action(entry->irq + i));



	pci_msi_teardown_msi_irqs(dev);



	list_for_each_entry_safe(entry, tmp, msi_list, list) {

		if (entry->msi_attrib.is_msix) {

			if (list_is_last(&entry->list, msi_list))

				iounmap(entry->mask_base);

		}



		list_del(&entry->list);

		free_msi_entry(entry);

	}



	if (dev->msi_irq_groups) {

		sysfs_remove_groups(&dev->dev.kobj, dev->msi_irq_groups);

		msi_attrs = dev->msi_irq_groups[0]->attrs;
@@ -421,6 +409,18 @@ static void free_msi_irqs(struct pci_dev *dev) 
		kfree(dev->msi_irq_groups);

		dev->msi_irq_groups = NULL;

	}



	pci_msi_teardown_msi_irqs(dev);



	list_for_each_entry_safe(entry, tmp, msi_list, list) {

		if (entry->msi_attrib.is_msix) {

			if (list_is_last(&entry->list, msi_list))

				iounmap(entry->mask_base);

		}



		list_del(&entry->list);

		free_msi_entry(entry);

	}

}



static void pci_intx_for_msi(struct pci_dev *dev, int enable)
@@ -590,6 +590,9 @@ msi_setup_entry(struct pci_dev *dev, int nvec, struct irq_affinity *affd) 
		goto out;



	pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);

	/* Lies, damned lies, and MSIs */

	if (dev->dev_flags & PCI_DEV_FLAGS_HAS_MSI_MASKING)

		control |= PCI_MSI_FLAGS_MASKBIT;



	entry->msi_attrib.is_msix	= 0;

	entry->msi_attrib.is_64		= !!(control & PCI_MSI_FLAGS_64BIT);

drivers/pci/quirks.c

+6 −0
Original line number Diff line number Diff line
@@ -5777,3 +5777,9 @@ static void apex_pci_fixup_class(struct pci_dev *pdev) 
}

DECLARE_PCI_FIXUP_CLASS_HEADER(0x1ac1, 0x089a,

			       PCI_CLASS_NOT_DEFINED, 8, apex_pci_fixup_class);



static void nvidia_ion_ahci_fixup(struct pci_dev *pdev)

{

	pdev->dev_flags |= PCI_DEV_FLAGS_HAS_MSI_MASKING;

}

DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, 0x0ab8, nvidia_ion_ahci_fixup);