Merge "msm: kgsl: Use booleans for power control features" (262793ca) · Commits · e / devices / android_kernel_fairphone_FP5

drivers/gpu/msm/adreno-gpulist.h

+0 −23

Original line number	Original line	Diff line number	Diff line
	@@ -28,7 +28,6 @@ static const struct adreno_a3xx_core adreno_gpu_core_a306 = {
	.gpudev = &adreno_a3xx_gpudev,		.gpudev = &adreno_a3xx_gpudev,
	.gmem_base = 0,		.gmem_base = 0,
	.gmem_size = SZ_128K,		.gmem_size = SZ_128K,
	.busy_mask = 0x7ffffffe,
	.bus_width = 0,		.bus_width = 0,
	.snapshot_size = 600 * SZ_1K,		.snapshot_size = 600 * SZ_1K,
	},		},
	@@ -51,7 +50,6 @@ static const struct adreno_a3xx_core adreno_gpu_core_a306a = {
	.gpudev = &adreno_a3xx_gpudev,		.gpudev = &adreno_a3xx_gpudev,
	.gmem_base = 0,		.gmem_base = 0,
	.gmem_size = SZ_128K,		.gmem_size = SZ_128K,
	.busy_mask = 0x7ffffffe,
	.bus_width = 16,		.bus_width = 16,
	.snapshot_size = 600 * SZ_1K,		.snapshot_size = 600 * SZ_1K,
	},		},
	@@ -72,7 +70,6 @@ static const struct adreno_a3xx_core adreno_gpu_core_a304 = {
	.gpudev = &adreno_a3xx_gpudev,		.gpudev = &adreno_a3xx_gpudev,
	.gmem_base = 0,		.gmem_base = 0,
	.gmem_size = (SZ_64K + SZ_32K),		.gmem_size = (SZ_64K + SZ_32K),
	.busy_mask = 0x7ffffffe,
	.bus_width = 0,		.bus_width = 0,
	.snapshot_size = 600 * SZ_1K,		.snapshot_size = 600 * SZ_1K,
	},		},
	@@ -197,7 +194,6 @@ static const struct adreno_a5xx_core adreno_gpu_core_a530v2 = {
	.gpudev = &adreno_a5xx_gpudev,		.gpudev = &adreno_a5xx_gpudev,
	.gmem_base = 0x100000,		.gmem_base = 0x100000,
	.gmem_size = SZ_1M,		.gmem_size = SZ_1M,
	.busy_mask = 0xfffffffe,
	.bus_width = 32,		.bus_width = 32,
	.snapshot_size = SZ_1M,		.snapshot_size = SZ_1M,
	},		},
	@@ -224,7 +220,6 @@ static const struct adreno_a5xx_core adreno_gpu_core_a530v3 = {
	.gpudev = &adreno_a5xx_gpudev,		.gpudev = &adreno_a5xx_gpudev,
	.gmem_base = 0x100000,		.gmem_base = 0x100000,
	.gmem_size = SZ_1M,		.gmem_size = SZ_1M,
	.busy_mask = 0xfffffffe,
	.bus_width = 32,		.bus_width = 32,
	.snapshot_size = SZ_1M,		.snapshot_size = SZ_1M,
	},		},
	@@ -291,7 +286,6 @@ static const struct adreno_a5xx_core adreno_gpu_core_a505 = {
	.gpudev = &adreno_a5xx_gpudev,		.gpudev = &adreno_a5xx_gpudev,
	.gmem_base = 0x100000,		.gmem_base = 0x100000,
	.gmem_size = (SZ_128K + SZ_8K),		.gmem_size = (SZ_128K + SZ_8K),
	.busy_mask = 0xfffffffe,
	.bus_width = 16,		.bus_width = 16,
	.snapshot_size = SZ_1M,		.snapshot_size = SZ_1M,
	},		},
	@@ -311,7 +305,6 @@ static const struct adreno_a5xx_core adreno_gpu_core_a506 = {
	.gpudev = &adreno_a5xx_gpudev,		.gpudev = &adreno_a5xx_gpudev,
	.gmem_base = 0x100000,		.gmem_base = 0x100000,
	.gmem_size = (SZ_128K + SZ_8K),		.gmem_size = (SZ_128K + SZ_8K),
	.busy_mask = 0xfffffffe,
	.bus_width = 16,		.bus_width = 16,
	.snapshot_size = SZ_1M,		.snapshot_size = SZ_1M,
	},		},
	@@ -390,7 +383,6 @@ static const struct adreno_a5xx_core adreno_gpu_core_a510 = {
	.gpudev = &adreno_a5xx_gpudev,		.gpudev = &adreno_a5xx_gpudev,
	.gmem_base = 0x100000,		.gmem_base = 0x100000,
	.gmem_size = SZ_256K,		.gmem_size = SZ_256K,
	.busy_mask = 0xfffffffe,
	.bus_width = 16,		.bus_width = 16,
	.snapshot_size = SZ_1M,		.snapshot_size = SZ_1M,
	},		},
	@@ -516,7 +508,6 @@ static const struct adreno_a5xx_core adreno_gpu_core_a540v2 = {
	.gpudev = &adreno_a5xx_gpudev,		.gpudev = &adreno_a5xx_gpudev,
	.gmem_base = 0x100000,		.gmem_base = 0x100000,
	.gmem_size = SZ_1M,		.gmem_size = SZ_1M,
	.busy_mask = 0xfffffffe,
	.bus_width = 32,		.bus_width = 32,
	.snapshot_size = SZ_1M,		.snapshot_size = SZ_1M,
	},		},
	@@ -600,7 +591,6 @@ static const struct adreno_a5xx_core adreno_gpu_core_a512 = {
	.gpudev = &adreno_a5xx_gpudev,		.gpudev = &adreno_a5xx_gpudev,
	.gmem_base = 0x100000,		.gmem_base = 0x100000,
	.gmem_size = (SZ_256K + SZ_16K),		.gmem_size = (SZ_256K + SZ_16K),
	.busy_mask = 0xfffffffe,
	.bus_width = 32,		.bus_width = 32,
	.snapshot_size = SZ_1M,		.snapshot_size = SZ_1M,
	},		},
	@@ -620,7 +610,6 @@ static const struct adreno_a5xx_core adreno_gpu_core_a508 = {
	.gpudev = &adreno_a5xx_gpudev,		.gpudev = &adreno_a5xx_gpudev,
	.gmem_base = 0x100000,		.gmem_base = 0x100000,
	.gmem_size = (SZ_128K + SZ_8K),		.gmem_size = (SZ_128K + SZ_8K),
	.busy_mask = 0xfffffffe,
	.bus_width = 32,		.bus_width = 32,
	.snapshot_size = SZ_1M,		.snapshot_size = SZ_1M,
	},		},
	@@ -796,7 +785,6 @@ static const struct adreno_a6xx_core adreno_gpu_core_a630v2 = {
	.gpudev = &adreno_a6xx_gpudev,		.gpudev = &adreno_a6xx_gpudev,
	.gmem_base = 0x100000,		.gmem_base = 0x100000,
	.gmem_size = SZ_1M,		.gmem_size = SZ_1M,
	.busy_mask = 0xfffffffe,
	.bus_width = 32,		.bus_width = 32,
	.snapshot_size = SZ_1M,		.snapshot_size = SZ_1M,
	},		},
	@@ -897,7 +885,6 @@ static const struct adreno_a6xx_core adreno_gpu_core_a615 = {
	.gpudev = &adreno_a6xx_gpudev,		.gpudev = &adreno_a6xx_gpudev,
	.gmem_base = 0x100000,		.gmem_base = 0x100000,
	.gmem_size = SZ_512K,		.gmem_size = SZ_512K,
	.busy_mask = 0xfffffffe,
	.bus_width = 32,		.bus_width = 32,
	.snapshot_size = 600 * SZ_1K,		.snapshot_size = 600 * SZ_1K,
	},		},
	@@ -926,7 +913,6 @@ static const struct adreno_a6xx_core adreno_gpu_core_a618 = {
	.gpudev = &adreno_a6xx_gpudev,		.gpudev = &adreno_a6xx_gpudev,
	.gmem_base = 0x100000,		.gmem_base = 0x100000,
	.gmem_size = SZ_512K,		.gmem_size = SZ_512K,
	.busy_mask = 0xfffffffe,
	.bus_width = 32,		.bus_width = 32,
	.snapshot_size = SZ_1M,		.snapshot_size = SZ_1M,
	},		},
	@@ -1056,7 +1042,6 @@ static const struct adreno_a6xx_core adreno_gpu_core_a620 = {
	.gpudev = &adreno_a6xx_gpudev,		.gpudev = &adreno_a6xx_gpudev,
	.gmem_base = 0,		.gmem_base = 0,
	.gmem_size = SZ_512K,		.gmem_size = SZ_512K,
	.busy_mask = 0xfffffffe,
	.bus_width = 32,		.bus_width = 32,
	.snapshot_size = 2 * SZ_1M,		.snapshot_size = 2 * SZ_1M,
	},		},
	@@ -1148,7 +1133,6 @@ static const struct adreno_a6xx_core adreno_gpu_core_a640 = {
	.gpudev = &adreno_a6xx_gpudev,		.gpudev = &adreno_a6xx_gpudev,
	.gmem_base = 0x100000,		.gmem_base = 0x100000,
	.gmem_size = SZ_1M, //Verified 1MB		.gmem_size = SZ_1M, //Verified 1MB
	.busy_mask = 0xfffffffe,
	.bus_width = 32,		.bus_width = 32,
	.snapshot_size = 2 * SZ_1M,		.snapshot_size = 2 * SZ_1M,
	},		},
	@@ -1230,7 +1214,6 @@ static const struct adreno_a6xx_core adreno_gpu_core_a650 = {
	.gpudev = &adreno_a6xx_gpudev,		.gpudev = &adreno_a6xx_gpudev,
	.gmem_base = 0,		.gmem_base = 0,
	.gmem_size = SZ_1M + SZ_128K, /* verified 1152kB */		.gmem_size = SZ_1M + SZ_128K, /* verified 1152kB */
	.busy_mask = 0xfffffffe,
	.bus_width = 32,		.bus_width = 32,
	.snapshot_size = 2 * SZ_1M,		.snapshot_size = 2 * SZ_1M,
	},		},
	@@ -1261,7 +1244,6 @@ static const struct adreno_a6xx_core adreno_gpu_core_a650v2 = {
	.gpudev = &adreno_a6xx_gpudev,		.gpudev = &adreno_a6xx_gpudev,
	.gmem_base = 0,		.gmem_base = 0,
	.gmem_size = SZ_1M + SZ_128K, /* verified 1152kB */		.gmem_size = SZ_1M + SZ_128K, /* verified 1152kB */
	.busy_mask = 0xfffffffe,
	.bus_width = 32,		.bus_width = 32,
	.snapshot_size = 2 * SZ_1M,		.snapshot_size = 2 * SZ_1M,
	},		},
	@@ -1289,7 +1271,6 @@ static const struct adreno_a6xx_core adreno_gpu_core_a680 = {
	.gpudev = &adreno_a6xx_gpudev,		.gpudev = &adreno_a6xx_gpudev,
	.gmem_base = 0x100000,		.gmem_base = 0x100000,
	.gmem_size = SZ_2M,		.gmem_size = SZ_2M,
	.busy_mask = 0xfffffffe,
	.bus_width = 32,		.bus_width = 32,
	.snapshot_size = SZ_1M,		.snapshot_size = SZ_1M,
	},		},
	@@ -1368,7 +1349,6 @@ static const struct adreno_a6xx_core adreno_gpu_core_a612 = {
	.gpudev = &adreno_a6xx_gpudev,		.gpudev = &adreno_a6xx_gpudev,
	.gmem_base = 0x100000,		.gmem_base = 0x100000,
	.gmem_size = (SZ_128K + SZ_4K),		.gmem_size = (SZ_128K + SZ_4K),
	.busy_mask = 0xfffffffe,
	.bus_width = 32,		.bus_width = 32,
	.snapshot_size = SZ_1M,		.snapshot_size = SZ_1M,
	},		},
	@@ -1395,7 +1375,6 @@ static const struct adreno_a6xx_core adreno_gpu_core_a616 = {
	.gpudev = &adreno_a6xx_gpudev,		.gpudev = &adreno_a6xx_gpudev,
	.gmem_base = 0x100000,		.gmem_base = 0x100000,
	.gmem_size = SZ_512K,		.gmem_size = SZ_512K,
	.busy_mask = 0xfffffffe,
	.bus_width = 32,		.bus_width = 32,
	.snapshot_size = SZ_1M,		.snapshot_size = SZ_1M,
	},		},
	@@ -1423,7 +1402,6 @@ static const struct adreno_a6xx_core adreno_gpu_core_a610 = {
	.gpudev = &adreno_a6xx_gpudev,		.gpudev = &adreno_a6xx_gpudev,
	.gmem_base = 0x100000,		.gmem_base = 0x100000,
	.gmem_size = (SZ_128K + SZ_4K),		.gmem_size = (SZ_128K + SZ_4K),
	.busy_mask = 0xfffffffe,
	.bus_width = 32,		.bus_width = 32,
	},		},
	.prim_fifo_threshold = 0x00080000,		.prim_fifo_threshold = 0x00080000,
	@@ -1537,7 +1515,6 @@ static const struct adreno_a6xx_core adreno_gpu_core_a660 = {
	.gpudev = &adreno_a6xx_gpudev,		.gpudev = &adreno_a6xx_gpudev,
	.gmem_base = 0,		.gmem_base = 0,
	.gmem_size = SZ_1M + SZ_512K,		.gmem_size = SZ_1M + SZ_512K,
	.busy_mask = 0xfffffffe,
	.bus_width = 32,		.bus_width = 32,
	.snapshot_size = SZ_1M,		.snapshot_size = SZ_1M,
	},		},

drivers/gpu/msm/adreno.c

+49 −113

Original line number	Original line	Diff line number	Diff line
	@@ -31,6 +31,7 @@
	#include "adreno-gpulist.h"		#include "adreno-gpulist.h"

	static void adreno_input_work(struct work_struct *work);		static void adreno_input_work(struct work_struct *work);
			static int adreno_soft_reset(struct kgsl_device *device);
	static unsigned int counter_delta(struct kgsl_device *device,		static unsigned int counter_delta(struct kgsl_device *device,
	unsigned int reg, unsigned int *counter);		unsigned int reg, unsigned int *counter);

	@@ -500,7 +501,7 @@ static struct input_handler adreno_input_handler = {
	* all the HW logic, restores GPU registers to default state and		* all the HW logic, restores GPU registers to default state and
	* flushes out pending VBIF transactions.		* flushes out pending VBIF transactions.
	*/		*/
	static int _soft_reset(struct adreno_device *adreno_dev)		static void _soft_reset(struct adreno_device *adreno_dev)
	{		{
	struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);		struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
	unsigned int reg;		unsigned int reg;
	@@ -517,8 +518,6 @@ static int _soft_reset(struct adreno_device *adreno_dev)

	if (gpudev->regulator_enable)		if (gpudev->regulator_enable)
	gpudev->regulator_enable(adreno_dev);		gpudev->regulator_enable(adreno_dev);

	return 0;
	}		}

	/**		/**
	@@ -986,7 +985,7 @@ static void adreno_of_get_limits(struct adreno_device *adreno_dev,
	pwrctrl->throttle_mask = GENMASK(pwrctrl->num_pwrlevels - 1,		pwrctrl->throttle_mask = GENMASK(pwrctrl->num_pwrlevels - 1,
	pwrctrl->num_pwrlevels - 1 - throttle_level);		pwrctrl->num_pwrlevels - 1 - throttle_level);

	set_bit(ADRENO_LM_CTRL, &adreno_dev->pwrctrl_flag);		adreno_dev->lm_enabled = true;
	}		}

	static int adreno_of_get_legacy_pwrlevels(struct adreno_device *adreno_dev,		static int adreno_of_get_legacy_pwrlevels(struct adreno_device *adreno_dev,
	@@ -1364,13 +1363,6 @@ static void adreno_setup_device(struct adreno_device *adreno_dev)

	INIT_WORK(&adreno_dev->input_work, adreno_input_work);		INIT_WORK(&adreno_dev->input_work, adreno_input_work);

	/*
	* Enable SPTP power collapse, throttling and hardware clock gating by
	* default where applicable
	*/
	adreno_dev->pwrctrl_flag = BIT(ADRENO_SPTP_PC_CTRL) \|
	BIT(ADRENO_THROTTLING_CTRL) \| BIT(ADRENO_HWCG_CTRL);

	INIT_LIST_HEAD(&adreno_dev->active_list);		INIT_LIST_HEAD(&adreno_dev->active_list);
	spin_lock_init(&adreno_dev->active_list_lock);		spin_lock_init(&adreno_dev->active_list_lock);

	@@ -2315,28 +2307,21 @@ static int adreno_stop(struct kgsl_device *device)
	int adreno_reset(struct kgsl_device *device, int fault)		int adreno_reset(struct kgsl_device *device, int fault)
	{		{
	struct adreno_device *adreno_dev = ADRENO_DEVICE(device);		struct adreno_device *adreno_dev = ADRENO_DEVICE(device);
			struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
	int ret = -EINVAL;		int ret = -EINVAL;
	int i = 0;		int i;

			if (gpudev->reset)
			return gpudev->reset(device, fault);

	/*		/*
	* Try soft reset first Do not do soft reset for a IOMMU fault (because		* Try soft reset first Do not do soft reset for a IOMMU fault (because
	* the IOMMU hardware needs a reset too) or for the A304 because it		* the IOMMU hardware needs a reset too)
	* can't do SMMU programming of any kind after a soft reset
	*/		*/

	if (!(fault & ADRENO_IOMMU_PAGE_FAULT) && !adreno_is_a304(adreno_dev)		if (!(fault & ADRENO_IOMMU_PAGE_FAULT))
	&& !adreno_is_a612(adreno_dev) && !adreno_is_a610(adreno_dev)) {
	/* Make sure VBIF is cleared before resetting */
	ret = adreno_clear_pending_transactions(device);

	if (ret == 0) {
	ret = adreno_soft_reset(device);		ret = adreno_soft_reset(device);
	if (ret)
	dev_err(device->dev,
	"Device soft reset failed: ret=%d\n",
	ret);
	}
	}
	if (ret) {		if (ret) {
	/* If soft reset failed/skipped, then pull the power */		/* If soft reset failed/skipped, then pull the power */
	kgsl_pwrctrl_change_state(device, KGSL_STATE_INIT);		kgsl_pwrctrl_change_state(device, KGSL_STATE_INIT);
	@@ -2346,22 +2331,18 @@ int adreno_reset(struct kgsl_device *device, int fault)
	/* Try to reset the device */		/* Try to reset the device */
	ret = adreno_start(device, 0);		ret = adreno_start(device, 0);

	/* On some GPUS, keep trying until it works */		for (i = 0; ret && i < NUM_TIMES_RESET_RETRY; i++) {
	if (ret && ADRENO_GPUREV(adreno_dev) < 600) {
	for (i = 0; i < NUM_TIMES_RESET_RETRY; i++) {
	msleep(20);		msleep(20);
	ret = adreno_start(device, 0);		ret = adreno_start(device, 0);
	if (!ret)
	break;
	}
	}
	}		}

	if (ret)		if (ret)
	return ret;		return ret;

	if (i != 0)		if (i != 0)
	dev_warn(device->dev,		dev_warn(device->dev,
	"Device hard reset tried %d tries\n", i);		"Device hard reset tried %d tries\n", i);
			}

	/*		/*
	* If active_cnt is non-zero then the system was active before		* If active_cnt is non-zero then the system was active before
	@@ -2752,7 +2733,7 @@ static int adreno_setproperty(struct kgsl_device_private *dev_priv,
	*		*
	* Returns true if interrupts are pending from device else 0.		* Returns true if interrupts are pending from device else 0.
	*/		*/
	inline unsigned int adreno_irq_pending(struct adreno_device *adreno_dev)		bool adreno_irq_pending(struct adreno_device *adreno_dev)
	{		{
	unsigned int status;		unsigned int status;

	@@ -2767,67 +2748,37 @@ inline unsigned int adreno_irq_pending(struct adreno_device *adreno_dev)
	*/		*/
	if ((status & adreno_dev->irq_mask) \|\|		if ((status & adreno_dev->irq_mask) \|\|
	atomic_read(&adreno_dev->pending_irq_refcnt))		atomic_read(&adreno_dev->pending_irq_refcnt))
	return 1;		return true;
	else
	return 0;
	}


	/**
	* adreno_hw_isidle() - Check if the GPU core is idle
	* @adreno_dev: Pointer to the Adreno device structure for the GPU
	*
	* Return true if the RBBM status register for the GPU type indicates that the
	* hardware is idle
	*/
	bool adreno_hw_isidle(struct adreno_device *adreno_dev)
	{
	const struct adreno_gpu_core *gpucore = adreno_dev->gpucore;
	unsigned int reg_rbbm_status;
	struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);

	/* if hw driver implements idle check - use it */
	if (gpudev->hw_isidle)
	return gpudev->hw_isidle(adreno_dev);

	if (adreno_is_a540(adreno_dev))
	/**
	* Due to CRC idle throttling GPU
	* idle hysteresys can take up to
	* 3usec for expire - account for it
	*/
	udelay(5);

	adreno_readreg(adreno_dev, ADRENO_REG_RBBM_STATUS,
	&reg_rbbm_status);

	if (reg_rbbm_status & gpucore->busy_mask)
	return false;

	/* Don't consider ourselves idle if there is an IRQ pending */
	if (adreno_irq_pending(adreno_dev))
	return false;		return false;

	return true;
	}		}

	/**		/*
	* adreno_soft_reset() - Do a soft reset of the GPU hardware		* adreno_soft_reset - Do a soft reset of the GPU hardware
	* @device: KGSL device to soft reset		* @device: KGSL device to soft reset
	*		*
	* "soft reset" the GPU hardware - this is a fast path GPU reset		* "soft reset" the GPU hardware - this is a fast path GPU reset
	* The GPU hardware is reset but we never pull power so we can skip		* The GPU hardware is reset but we never pull power so we can skip
	* a lot of the standard adreno_stop/adreno_start sequence		* a lot of the standard adreno_stop/adreno_start sequence
	*/		*/
	int adreno_soft_reset(struct kgsl_device *device)		static int adreno_soft_reset(struct kgsl_device *device)
	{		{
	struct adreno_device *adreno_dev = ADRENO_DEVICE(device);		struct adreno_device *adreno_dev = ADRENO_DEVICE(device);
	struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);		struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
	int ret;		int ret;

	ret = gmu_core_dev_oob_set(device, oob_gpu);		/*
	if (ret)		* Don't allow a soft reset for a304 because the SMMU needs to be hard
			* reset
			*/
			if (adreno_is_a304(adreno_dev))
			return -ENODEV;

			ret = adreno_clear_pending_transactions(device);
			if (ret) {
			dev_err(device->dev, "Timed out while clearing the VBIF\n");
	return ret;		return ret;
			}

	kgsl_pwrctrl_change_state(device, KGSL_STATE_AWARE);		kgsl_pwrctrl_change_state(device, KGSL_STATE_AWARE);
	adreno_set_active_ctxs_null(adreno_dev);		adreno_set_active_ctxs_null(adreno_dev);
	@@ -2841,15 +2792,7 @@ int adreno_soft_reset(struct kgsl_device *device)
	/* save physical performance counter values before GPU soft reset */		/* save physical performance counter values before GPU soft reset */
	adreno_perfcounter_save(adreno_dev);		adreno_perfcounter_save(adreno_dev);

	/* Reset the GPU */		_soft_reset(adreno_dev);
	if (gpudev->soft_reset)
	ret = gpudev->soft_reset(adreno_dev);
	else
	ret = _soft_reset(adreno_dev);
	if (ret) {
	gmu_core_dev_oob_clear(device, oob_gpu);
	return ret;
	}

	/* Clear the busy_data stats - we're starting over from scratch */		/* Clear the busy_data stats - we're starting over from scratch */
	adreno_dev->busy_data.gpu_busy = 0;		adreno_dev->busy_data.gpu_busy = 0;
	@@ -2889,25 +2832,19 @@ int adreno_soft_reset(struct kgsl_device *device)
	/* Restore physical performance counter values after soft reset */		/* Restore physical performance counter values after soft reset */
	adreno_perfcounter_restore(adreno_dev);		adreno_perfcounter_restore(adreno_dev);

	gmu_core_dev_oob_clear(device, oob_gpu);		if (ret)
			dev_err(device->dev, "Device soft reset failed: %d\n", ret);

	return ret;		return ret;
	}		}

	/*		static bool adreno_isidle(struct adreno_device *adreno_dev)
	* adreno_isidle() - return true if the GPU hardware is idle
	* @device: Pointer to the KGSL device structure for the GPU
	*
	* Return true if the GPU hardware is idle and there are no commands pending in
	* the ringbuffer
	*/
	bool adreno_isidle(struct kgsl_device *device)
	{		{
	struct adreno_device *adreno_dev = ADRENO_DEVICE(device);		struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
	struct adreno_ringbuffer *rb;		struct adreno_ringbuffer *rb;
	int i;		int i;

	if (!kgsl_state_is_awake(device))		if (!kgsl_state_is_awake(KGSL_DEVICE(adreno_dev)))
	return true;		return true;

	/*		/*
	@@ -2926,7 +2863,7 @@ bool adreno_isidle(struct kgsl_device *device)
	return false;		return false;
	}		}

	return adreno_hw_isidle(adreno_dev);		return gpudev->hw_isidle(adreno_dev);
	}		}

	/* Print some key registers if a spin-for-idle times out */		/* Print some key registers if a spin-for-idle times out */
	@@ -2987,7 +2924,7 @@ int adreno_spin_idle(struct adreno_device *adreno_dev, unsigned int timeout)
	if (adreno_gpu_fault(adreno_dev) != 0)		if (adreno_gpu_fault(adreno_dev) != 0)
	return -EDEADLK;		return -EDEADLK;

	if (adreno_isidle(KGSL_DEVICE(adreno_dev)))		if (adreno_isidle(adreno_dev))
	return 0;		return 0;

	} while (time_before(jiffies, wait));		} while (time_before(jiffies, wait));
	@@ -3000,7 +2937,7 @@ int adreno_spin_idle(struct adreno_device *adreno_dev, unsigned int timeout)
	if (adreno_gpu_fault(adreno_dev) != 0)		if (adreno_gpu_fault(adreno_dev) != 0)
	return -EDEADLK;		return -EDEADLK;

	if (adreno_isidle(KGSL_DEVICE(adreno_dev)))		if (adreno_isidle(adreno_dev))
	return 0;		return 0;

	return -ETIMEDOUT;		return -ETIMEDOUT;
	@@ -3028,7 +2965,7 @@ int adreno_idle(struct kgsl_device *device)
	return -EDEADLK;		return -EDEADLK;

	/* Check if we are already idle before idling dispatcher */		/* Check if we are already idle before idling dispatcher */
	if (adreno_isidle(device))		if (adreno_isidle(adreno_dev))
	return 0;		return 0;
	/*		/*
	* Wait for dispatcher to finish completing commands		* Wait for dispatcher to finish completing commands
	@@ -3725,7 +3662,7 @@ static bool adreno_is_hw_collapsible(struct kgsl_device *device)
	device->pwrctrl.ctrl_flags)		device->pwrctrl.ctrl_flags)
	return false;		return false;

	return adreno_isidle(device) && (gpudev->is_sptp_idle ?		return adreno_isidle(adreno_dev) && (gpudev->is_sptp_idle ?
	gpudev->is_sptp_idle(adreno_dev) : true);		gpudev->is_sptp_idle(adreno_dev) : true);
	}		}

	@@ -3789,7 +3726,7 @@ static bool adreno_is_hwcg_on(struct kgsl_device *device)
	{		{
	struct adreno_device *adreno_dev = ADRENO_DEVICE(device);		struct adreno_device *adreno_dev = ADRENO_DEVICE(device);

	return test_bit(ADRENO_HWCG_CTRL, &adreno_dev->pwrctrl_flag);		return adreno_dev->hwcg_enabled;
	}		}

	static int adreno_queue_cmds(struct kgsl_device_private *dev_priv,		static int adreno_queue_cmds(struct kgsl_device_private *dev_priv,
	@@ -3811,7 +3748,6 @@ static const struct kgsl_functable adreno_functable = {
	.regread = adreno_regread,		.regread = adreno_regread,
	.regwrite = adreno_regwrite,		.regwrite = adreno_regwrite,
	.idle = adreno_idle,		.idle = adreno_idle,
	.isidle = adreno_isidle,
	.suspend_context = adreno_suspend_context,		.suspend_context = adreno_suspend_context,
	.first_open = adreno_first_open,		.first_open = adreno_first_open,
	.start = adreno_start,		.start = adreno_start,

drivers/gpu/msm/adreno.h

+17 −18

Original line number	Original line	Diff line number	Diff line
	@@ -206,12 +206,6 @@ enum adreno_gpurev {
	#define ADRENO_CTX_DETATCH_TIMEOUT_FAULT BIT(6)		#define ADRENO_CTX_DETATCH_TIMEOUT_FAULT BIT(6)
	#define ADRENO_GMU_FAULT_SKIP_SNAPSHOT BIT(7)		#define ADRENO_GMU_FAULT_SKIP_SNAPSHOT BIT(7)

	#define ADRENO_SPTP_PC_CTRL 0
	#define ADRENO_LM_CTRL 1
	#define ADRENO_HWCG_CTRL 2
	#define ADRENO_THROTTLING_CTRL 3
	#define ADRENO_ACD_CTRL 4

	/* VBIF, GBIF halt request and ack mask */		/* VBIF, GBIF halt request and ack mask */
	#define GBIF_HALT_REQUEST 0x1E0		#define GBIF_HALT_REQUEST 0x1E0
	#define VBIF_RESET_ACK_MASK 0x00f0		#define VBIF_RESET_ACK_MASK 0x00f0
	@@ -340,7 +334,6 @@ struct adreno_reglist {
	* @gpudev: Pointer to the GPU family specific functions for this core		* @gpudev: Pointer to the GPU family specific functions for this core
	* @gmem_base: Base address of binning memory (GMEM/OCMEM)		* @gmem_base: Base address of binning memory (GMEM/OCMEM)
	* @gmem_size: Amount of binning memory (GMEM/OCMEM) to reserve for the core		* @gmem_size: Amount of binning memory (GMEM/OCMEM) to reserve for the core
	* @busy_mask: mask to check if GPU is busy in RBBM_STATUS
	* @bus_width: Bytes transferred in 1 cycle		* @bus_width: Bytes transferred in 1 cycle
	*/		*/
	struct adreno_gpu_core {		struct adreno_gpu_core {
	@@ -350,7 +343,6 @@ struct adreno_gpu_core {
	struct adreno_gpudev *gpudev;		struct adreno_gpudev *gpudev;
	unsigned long gmem_base;		unsigned long gmem_base;
	size_t gmem_size;		size_t gmem_size;
	unsigned int busy_mask;
	u32 bus_width;		u32 bus_width;
	/** @snapshot_size: Size of the static snapshot region in bytes */		/** @snapshot_size: Size of the static snapshot region in bytes */
	u32 snapshot_size;		u32 snapshot_size;
	@@ -413,7 +405,6 @@ struct adreno_gpu_core {
	* @halt: Atomic variable to check whether the GPU is currently halted		* @halt: Atomic variable to check whether the GPU is currently halted
	* @pending_irq_refcnt: Atomic variable to keep track of running IRQ handlers		* @pending_irq_refcnt: Atomic variable to keep track of running IRQ handlers
	* @ctx_d_debugfs: Context debugfs node		* @ctx_d_debugfs: Context debugfs node
	* @pwrctrl_flag: Flag to hold adreno specific power attributes
	* @profile_buffer: Memdesc holding the drawobj profiling buffer		* @profile_buffer: Memdesc holding the drawobj profiling buffer
	* @profile_index: Index to store the start/stop ticks in the profiling		* @profile_index: Index to store the start/stop ticks in the profiling
	* buffer		* buffer
	@@ -485,8 +476,16 @@ struct adreno_device {
	atomic_t halt;		atomic_t halt;
	atomic_t pending_irq_refcnt;		atomic_t pending_irq_refcnt;
	struct dentry *ctx_d_debugfs;		struct dentry *ctx_d_debugfs;
	unsigned long pwrctrl_flag;		/** @lm_enabled: True if limits management is enabled for this target */
			bool lm_enabled;
			/** @acd_enabled: True if acd is enabled for this target */
			bool acd_enabled;
			/** @hwcg_enabled: True if hardware clock gating is enabled */
			bool hwcg_enabled;
			/** @throttling_enabled: True if LM throttling is enabled on a5xx */
			bool throttling_enabled;
			/** @sptp_pc_enabled: True if SPTP power collapse is enabled on a5xx */
			bool sptp_pc_enabled;
	struct kgsl_memdesc *profile_buffer;		struct kgsl_memdesc *profile_buffer;
	unsigned int profile_index;		unsigned int profile_index;
	struct kgsl_memdesc *pwrup_reglist;		struct kgsl_memdesc *pwrup_reglist;
	@@ -643,8 +642,6 @@ enum adreno_regs {
	ADRENO_REG_RBBM_INT_0_STATUS,		ADRENO_REG_RBBM_INT_0_STATUS,
	ADRENO_REG_RBBM_PM_OVERRIDE2,		ADRENO_REG_RBBM_PM_OVERRIDE2,
	ADRENO_REG_RBBM_SW_RESET_CMD,		ADRENO_REG_RBBM_SW_RESET_CMD,
	ADRENO_REG_RBBM_BLOCK_SW_RESET_CMD,
	ADRENO_REG_RBBM_BLOCK_SW_RESET_CMD2,
	ADRENO_REG_RBBM_CLOCK_CTL,		ADRENO_REG_RBBM_CLOCK_CTL,
	ADRENO_REG_PA_SC_AA_CONFIG,		ADRENO_REG_PA_SC_AA_CONFIG,
	ADRENO_REG_SQ_GPR_MANAGEMENT,		ADRENO_REG_SQ_GPR_MANAGEMENT,
	@@ -789,7 +786,6 @@ struct adreno_gpudev {
	const char (iommu_fault_block)(struct kgsl_device *device,		const char (iommu_fault_block)(struct kgsl_device *device,
	unsigned int fsynr1);		unsigned int fsynr1);
	int (reset)(struct kgsl_device device, int fault);		int (reset)(struct kgsl_device device, int fault);
	int (soft_reset)(struct adreno_device adreno_dev);
	bool (sptprac_is_on)(struct adreno_device adreno_dev);		bool (sptprac_is_on)(struct adreno_device adreno_dev);
	unsigned int (ccu_invalidate)(struct adreno_device adreno_dev,		unsigned int (ccu_invalidate)(struct adreno_device adreno_dev,
	unsigned int *cmds);		unsigned int *cmds);
	@@ -871,7 +867,6 @@ extern int adreno_wake_nice;
	extern unsigned int adreno_wake_timeout;		extern unsigned int adreno_wake_timeout;

	int adreno_start(struct kgsl_device *device, int priority);		int adreno_start(struct kgsl_device *device, int priority);
	int adreno_soft_reset(struct kgsl_device *device);
	long adreno_ioctl(struct kgsl_device_private *dev_priv,		long adreno_ioctl(struct kgsl_device_private *dev_priv,
	unsigned int cmd, unsigned long arg);		unsigned int cmd, unsigned long arg);

	@@ -893,7 +888,6 @@ int adreno_switch_to_unsecure_mode(struct adreno_device *adreno_dev,
	void adreno_spin_idle_debug(struct adreno_device adreno_dev, const char str);		void adreno_spin_idle_debug(struct adreno_device adreno_dev, const char str);
	int adreno_spin_idle(struct adreno_device *device, unsigned int timeout);		int adreno_spin_idle(struct adreno_device *device, unsigned int timeout);
	int adreno_idle(struct kgsl_device *device);		int adreno_idle(struct kgsl_device *device);
	bool adreno_isidle(struct kgsl_device *device);

	int adreno_set_constraint(struct kgsl_device *device,		int adreno_set_constraint(struct kgsl_device *device,
	struct kgsl_context *context,		struct kgsl_context *context,
	@@ -909,8 +903,6 @@ void adreno_fault_skipcmd_detached(struct adreno_device *adreno_dev,
	struct adreno_context *drawctxt,		struct adreno_context *drawctxt,
	struct kgsl_drawobj *drawobj);		struct kgsl_drawobj *drawobj);

	bool adreno_hw_isidle(struct adreno_device *adreno_dev);

	void adreno_fault_detect_start(struct adreno_device *adreno_dev);		void adreno_fault_detect_start(struct adreno_device *adreno_dev);
	void adreno_fault_detect_stop(struct adreno_device *adreno_dev);		void adreno_fault_detect_stop(struct adreno_device *adreno_dev);

	@@ -950,6 +942,13 @@ void adreno_rscc_regread(struct adreno_device *adreno_dev,
	void adreno_isense_regread(struct adreno_device *adreno_dev,		void adreno_isense_regread(struct adreno_device *adreno_dev,
	unsigned int offsetwords, unsigned int *value);		unsigned int offsetwords, unsigned int *value);

			/**
			* adreno_irq_pending - Return true if an interrupt is pending
			* @adreno_dev: An Adreno GPU device handle
			*
			* Returns: true if interrupts are pending on the device
			*/
			bool adreno_irq_pending(struct adreno_device *adreno_dev);

	#define ADRENO_TARGET(_name, _id) \		#define ADRENO_TARGET(_name, _id) \
	static inline int adreno_is_##_name(struct adreno_device *adreno_dev) \		static inline int adreno_is_##_name(struct adreno_device *adreno_dev) \

drivers/gpu/msm/adreno_a3xx.c

+14 −0

Original line number	Original line	Diff line number	Diff line
	@@ -1381,6 +1381,19 @@ static irqreturn_t a3xx_irq_handler(struct adreno_device *adreno_dev)
	return ret;		return ret;
	}		}

			static bool a3xx_hw_isidle(struct adreno_device *adreno_dev)
			{
			struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
			u32 status;

			kgsl_regread(device, A3XX_RBBM_STATUS, &status);

			if (status & 0x7ffffffe)
			return false;

			return adreno_irq_pending(adreno_dev) ? false : true;
			}

	struct adreno_gpudev adreno_a3xx_gpudev = {		struct adreno_gpudev adreno_a3xx_gpudev = {
	.reg_offsets = a3xx_register_offsets,		.reg_offsets = a3xx_register_offsets,
	.ft_perf_counters = a3xx_ft_perf_counters,		.ft_perf_counters = a3xx_ft_perf_counters,
	@@ -1399,4 +1412,5 @@ struct adreno_gpudev adreno_a3xx_gpudev = {
	#endif		#endif
	.clk_set_options = a3xx_clk_set_options,		.clk_set_options = a3xx_clk_set_options,
	.read_alwayson = a3xx_read_alwayson,		.read_alwayson = a3xx_read_alwayson,
			.hw_isidle = a3xx_hw_isidle,
	};		};

drivers/gpu/msm/adreno_a5xx.c

+44 −39

Original line number	Original line	Diff line number	Diff line
	@@ -89,7 +89,15 @@ static void a530_efuse_leakage(struct adreno_device *adreno_dev)

	static void a5xx_platform_setup(struct adreno_device *adreno_dev)		static void a5xx_platform_setup(struct adreno_device *adreno_dev)
	{		{
	set_bit(ADRENO_LM_CTRL, &adreno_dev->pwrctrl_flag);		adreno_dev->sptp_pc_enabled =
			ADRENO_FEATURE(adreno_dev, ADRENO_SPTP_PC);

			if (adreno_is_a540(adreno_dev))
			adreno_dev->throttling_enabled = true;

			adreno_dev->hwcg_enabled = true;
			adreno_dev->lm_enabled =
			ADRENO_FEATURE(adreno_dev, ADRENO_LM);

	/* Set the GPU busy counter to use for frequency scaling */		/* Set the GPU busy counter to use for frequency scaling */
	adreno_dev->perfctr_pwr_lo = A5XX_RBBM_PERFCTR_RBBM_0_LO;		adreno_dev->perfctr_pwr_lo = A5XX_RBBM_PERFCTR_RBBM_0_LO;
	@@ -261,8 +269,7 @@ static bool a5xx_is_sptp_idle(struct adreno_device *adreno_dev)
	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);		struct kgsl_device *device = KGSL_DEVICE(adreno_dev);

	/* If feature is not supported or enabled, no worry */		/* If feature is not supported or enabled, no worry */
	if (!ADRENO_FEATURE(adreno_dev, ADRENO_SPTP_PC) \|\|		if (!adreno_dev->sptp_pc_enabled)
	!test_bit(ADRENO_SPTP_PC_CTRL, &adreno_dev->pwrctrl_flag))
	return true;		return true;
	kgsl_regread(device, A5XX_GPMU_SP_PWR_CLK_STATUS, &reg);		kgsl_regread(device, A5XX_GPMU_SP_PWR_CLK_STATUS, &reg);
	if (reg & BIT(20))		if (reg & BIT(20))
	@@ -404,8 +411,7 @@ static void a5xx_regulator_disable(struct adreno_device *adreno_dev)
	return;		return;

	/* If feature is not supported or not enabled */		/* If feature is not supported or not enabled */
	if (!ADRENO_FEATURE(adreno_dev, ADRENO_SPTP_PC) \|\|		if (!adreno_dev->sptp_pc_enabled) {
	!test_bit(ADRENO_SPTP_PC_CTRL, &adreno_dev->pwrctrl_flag)) {
	/* Set the default register values; set SW_COLLAPSE to 1 */		/* Set the default register values; set SW_COLLAPSE to 1 */
	kgsl_regwrite(device, A5XX_GPMU_SP_POWER_CNTL, 0x778001);		kgsl_regwrite(device, A5XX_GPMU_SP_POWER_CNTL, 0x778001);
	/*		/*
	@@ -456,8 +462,7 @@ static void a5xx_enable_pc(struct adreno_device *adreno_dev)
	{		{
	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);		struct kgsl_device *device = KGSL_DEVICE(adreno_dev);

	if (!ADRENO_FEATURE(adreno_dev, ADRENO_SPTP_PC) \|\|		if (!adreno_dev->sptp_pc_enabled)
	!test_bit(ADRENO_SPTP_PC_CTRL, &adreno_dev->pwrctrl_flag))
	return;		return;

	kgsl_regwrite(device, A5XX_GPMU_PWR_COL_INTER_FRAME_CTRL, 0x0000007F);		kgsl_regwrite(device, A5XX_GPMU_PWR_COL_INTER_FRAME_CTRL, 0x0000007F);
	@@ -701,7 +706,7 @@ void a5xx_hwcg_set(struct adreno_device *adreno_dev, bool on)
	const struct adreno_a5xx_core *a5xx_core = to_a5xx_core(adreno_dev);		const struct adreno_a5xx_core *a5xx_core = to_a5xx_core(adreno_dev);
	int i;		int i;

	if (!test_bit(ADRENO_HWCG_CTRL, &adreno_dev->pwrctrl_flag))		if (!adreno_dev->hwcg_enabled)
	return;		return;

	for (i = 0; i < a5xx_core->hwcg_count; i++)		for (i = 0; i < a5xx_core->hwcg_count; i++)
	@@ -934,8 +939,7 @@ static void a530_lm_init(struct adreno_device *adreno_dev)
	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);		struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
	const struct adreno_a5xx_core *a5xx_core = to_a5xx_core(adreno_dev);		const struct adreno_a5xx_core *a5xx_core = to_a5xx_core(adreno_dev);

	if (!ADRENO_FEATURE(adreno_dev, ADRENO_LM) \|\|		if (!adreno_dev->lm_enabled)
	!test_bit(ADRENO_LM_CTRL, &adreno_dev->pwrctrl_flag))
	return;		return;

	/* If something was wrong with the sequence file, return */		/* If something was wrong with the sequence file, return */
	@@ -985,8 +989,7 @@ static void a530_lm_enable(struct adreno_device *adreno_dev)
	{		{
	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);		struct kgsl_device *device = KGSL_DEVICE(adreno_dev);

	if (!ADRENO_FEATURE(adreno_dev, ADRENO_LM) \|\|		if (!adreno_dev->lm_enabled)
	!test_bit(ADRENO_LM_CTRL, &adreno_dev->pwrctrl_flag))
	return;		return;

	/* If no sequence properly initialized, return */		/* If no sequence properly initialized, return */
	@@ -1015,10 +1018,10 @@ static void a540_lm_init(struct adreno_device *adreno_dev)
	<< AGC_GPU_VERSION_SHIFT);		<< AGC_GPU_VERSION_SHIFT);
	unsigned int r;		unsigned int r;

	if (!test_bit(ADRENO_THROTTLING_CTRL, &adreno_dev->pwrctrl_flag))		if (!adreno_dev->throttling_enabled)
	agc_lm_config \|= AGC_THROTTLE_DISABLE;		agc_lm_config \|= AGC_THROTTLE_DISABLE;

	if (lm_on(adreno_dev)) {		if (adreno_dev->lm_enabled) {
	agc_lm_config \|=		agc_lm_config \|=
	AGC_LM_CONFIG_ENABLE_GPMU_ADAPTIVE \|		AGC_LM_CONFIG_ENABLE_GPMU_ADAPTIVE \|
	AGC_LM_CONFIG_ISENSE_ENABLE;		AGC_LM_CONFIG_ISENSE_ENABLE;
	@@ -1096,20 +1099,11 @@ static void a5xx_pwrlevel_change_settings(struct adreno_device *adreno_dev,
	unsigned int prelevel, unsigned int postlevel,		unsigned int prelevel, unsigned int postlevel,
	bool post)		bool post)
	{		{
	int on = 0;		/*
			* On pre A540 HW only call through if LMx is supported and enabled, and
	/* On pre A540 HW only call through if LMx is supported and enabled */		* always call through for a540
	if (ADRENO_FEATURE(adreno_dev, ADRENO_LM) &&		*/
	test_bit(ADRENO_LM_CTRL, &adreno_dev->pwrctrl_flag))		if (!adreno_is_a540(adreno_dev) && !adreno_dev->lm_enabled)
	on = ADRENO_LM;

	/* On 540+ HW call through unconditionally as long as GPMU is enabled */
	if (ADRENO_FEATURE(adreno_dev, ADRENO_GPMU)) {
	if (adreno_is_a540(adreno_dev))
	on = ADRENO_GPMU;
	}

	if (!on)
	return;		return;

	if (!post) {		if (!post) {
	@@ -1158,13 +1152,7 @@ static int64_t a5xx_read_throttling_counters(struct adreno_device *adreno_dev)
	uint32_t th[ADRENO_GPMU_THROTTLE_COUNTERS];		uint32_t th[ADRENO_GPMU_THROTTLE_COUNTERS];
	struct adreno_busy_data *busy = &adreno_dev->busy_data;		struct adreno_busy_data *busy = &adreno_dev->busy_data;

	if (!adreno_is_a540(adreno_dev))		if (!adreno_dev->throttling_enabled)
	return 0;

	if (!ADRENO_FEATURE(adreno_dev, ADRENO_GPMU))
	return 0;

	if (!test_bit(ADRENO_THROTTLING_CTRL, &adreno_dev->pwrctrl_flag))
	return 0;		return 0;

	for (i = 0; i < ADRENO_GPMU_THROTTLE_COUNTERS; i++) {		for (i = 0; i < ADRENO_GPMU_THROTTLE_COUNTERS; i++) {
	@@ -2378,10 +2366,6 @@ static unsigned int a5xx_register_offsets[ADRENO_REG_REGISTER_MAX] = {
	ADRENO_REG_DEFINE(ADRENO_REG_RBBM_INT_0_STATUS, A5XX_RBBM_INT_0_STATUS),		ADRENO_REG_DEFINE(ADRENO_REG_RBBM_INT_0_STATUS, A5XX_RBBM_INT_0_STATUS),
	ADRENO_REG_DEFINE(ADRENO_REG_RBBM_CLOCK_CTL, A5XX_RBBM_CLOCK_CNTL),		ADRENO_REG_DEFINE(ADRENO_REG_RBBM_CLOCK_CTL, A5XX_RBBM_CLOCK_CNTL),
	ADRENO_REG_DEFINE(ADRENO_REG_RBBM_SW_RESET_CMD, A5XX_RBBM_SW_RESET_CMD),		ADRENO_REG_DEFINE(ADRENO_REG_RBBM_SW_RESET_CMD, A5XX_RBBM_SW_RESET_CMD),
	ADRENO_REG_DEFINE(ADRENO_REG_RBBM_BLOCK_SW_RESET_CMD,
	A5XX_RBBM_BLOCK_SW_RESET_CMD),
	ADRENO_REG_DEFINE(ADRENO_REG_RBBM_BLOCK_SW_RESET_CMD2,
	A5XX_RBBM_BLOCK_SW_RESET_CMD2),
	ADRENO_REG_DEFINE(ADRENO_REG_UCHE_INVALIDATE0, A5XX_UCHE_INVALIDATE0),		ADRENO_REG_DEFINE(ADRENO_REG_UCHE_INVALIDATE0, A5XX_UCHE_INVALIDATE0),
	ADRENO_REG_DEFINE(ADRENO_REG_RBBM_PERFCTR_RBBM_0_LO,		ADRENO_REG_DEFINE(ADRENO_REG_RBBM_PERFCTR_RBBM_0_LO,
	A5XX_RBBM_PERFCTR_RBBM_0_LO),		A5XX_RBBM_PERFCTR_RBBM_0_LO),
	@@ -2756,6 +2740,26 @@ static irqreturn_t a5xx_irq_handler(struct adreno_device *adreno_dev)
	return ret;		return ret;
	}		}

			static bool a5xx_hw_isidle(struct adreno_device *adreno_dev)
			{
			struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
			u32 status;

			/*
			* Due to CRC idle throttling the GPU idle hysteresis on a540 can take
			* up to 5uS to expire
			*/
			if (adreno_is_a540(adreno_dev))
			udelay(5);

			kgsl_regread(device, A5XX_RBBM_STATUS, &status);

			if (status & 0xfffffffe)
			return false;

			return adreno_irq_pending(adreno_dev) ? false : true;
			}

	#ifdef CONFIG_QCOM_KGSL_CORESIGHT		#ifdef CONFIG_QCOM_KGSL_CORESIGHT
	static struct adreno_coresight_register a5xx_coresight_registers[] = {		static struct adreno_coresight_register a5xx_coresight_registers[] = {
	{ A5XX_RBBM_CFG_DBGBUS_SEL_A },		{ A5XX_RBBM_CFG_DBGBUS_SEL_A },
	@@ -2982,4 +2986,5 @@ struct adreno_gpudev adreno_a5xx_gpudev = {
	.preemption_schedule = a5xx_preemption_schedule,		.preemption_schedule = a5xx_preemption_schedule,
	.clk_set_options = a5xx_clk_set_options,		.clk_set_options = a5xx_clk_set_options,
	.read_alwayson = a5xx_read_alwayson,		.read_alwayson = a5xx_read_alwayson,
			.hw_isidle = a5xx_hw_isidle,
	};		};