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Commit ed253b59 authored by Jordan Crouse's avatar Jordan Crouse
Browse files

msm: kgsl: Use booleans for power control features 



Currently we use a bitmask for the power control features (SPTP, ACD, LM,
etc).  Move to individual booleans for each feature instead. Booleans
are less unweidly to use and require less if () statements.

Additionally if we properly use the Adreno feature flags when setting
and/or modifying the booleans we can get rid of the feature flag checks in
the rest of the code and use the control booleans as they are intended.

And finally, move some of the target specific control features to the
target specific code. This ensures that the target specific code can
control the feature and the other targets don't accidentally specify
the wrong state through sysfs. For example, if SPTP power collapse is
only available for a5xx then the sysfs file should only ever return
false for the other targets.

Change-Id: Ic0dedbad1828ae9163a1a1357828156cb3281914
Signed-off-by: default avatarJordan Crouse <jcrouse@codeaurora.org>
parent 8152ccc9

drivers/gpu/msm/adreno.c

+2 −9
Original line number Diff line number Diff line
@@ -985,7 +985,7 @@ static void adreno_of_get_limits(struct adreno_device *adreno_dev, 
	pwrctrl->throttle_mask = GENMASK(pwrctrl->num_pwrlevels - 1,

			pwrctrl->num_pwrlevels - 1 - throttle_level);



	set_bit(ADRENO_LM_CTRL, &adreno_dev->pwrctrl_flag);

	adreno_dev->lm_enabled = true;

}



static int adreno_of_get_legacy_pwrlevels(struct adreno_device *adreno_dev,
@@ -1363,13 +1363,6 @@ static void adreno_setup_device(struct adreno_device *adreno_dev) 


	INIT_WORK(&adreno_dev->input_work, adreno_input_work);



	/*

	 * Enable SPTP power collapse, throttling and hardware clock gating by

	 * default where applicable

	 */

	adreno_dev->pwrctrl_flag = BIT(ADRENO_SPTP_PC_CTRL) |

		BIT(ADRENO_THROTTLING_CTRL) | BIT(ADRENO_HWCG_CTRL);



	INIT_LIST_HEAD(&adreno_dev->active_list);

	spin_lock_init(&adreno_dev->active_list_lock);
@@ -3733,7 +3726,7 @@ static bool adreno_is_hwcg_on(struct kgsl_device *device) 
{

	struct adreno_device *adreno_dev = ADRENO_DEVICE(device);



	return test_bit(ADRENO_HWCG_CTRL, &adreno_dev->pwrctrl_flag);

	return adreno_dev->hwcg_enabled;

}



static int adreno_queue_cmds(struct kgsl_device_private *dev_priv,

drivers/gpu/msm/adreno.h

+10 −9
Original line number Diff line number Diff line
@@ -206,12 +206,6 @@ enum adreno_gpurev { 
#define ADRENO_CTX_DETATCH_TIMEOUT_FAULT BIT(6)

#define ADRENO_GMU_FAULT_SKIP_SNAPSHOT BIT(7)



#define ADRENO_SPTP_PC_CTRL 0

#define ADRENO_LM_CTRL      1

#define ADRENO_HWCG_CTRL    2

#define ADRENO_THROTTLING_CTRL 3

#define ADRENO_ACD_CTRL 4



/* VBIF,  GBIF halt request and ack mask */

#define GBIF_HALT_REQUEST       0x1E0

#define VBIF_RESET_ACK_MASK     0x00f0
@@ -411,7 +405,6 @@ struct adreno_gpu_core { 
 * @halt: Atomic variable to check whether the GPU is currently halted

 * @pending_irq_refcnt: Atomic variable to keep track of running IRQ handlers

 * @ctx_d_debugfs: Context debugfs node

 * @pwrctrl_flag: Flag to hold adreno specific power attributes

 * @profile_buffer: Memdesc holding the drawobj profiling buffer

 * @profile_index: Index to store the start/stop ticks in the profiling

 * buffer
@@ -483,8 +476,16 @@ struct adreno_device { 
	atomic_t halt;

	atomic_t pending_irq_refcnt;

	struct dentry *ctx_d_debugfs;

	unsigned long pwrctrl_flag;



	/** @lm_enabled: True if limits management is enabled for this target */

	bool lm_enabled;

	/** @acd_enabled: True if acd is enabled for this target */

	bool acd_enabled;

	/** @hwcg_enabled: True if hardware clock gating is enabled */

	bool hwcg_enabled;

	/** @throttling_enabled: True if LM throttling is enabled on a5xx */

	bool throttling_enabled;

	/** @sptp_pc_enabled: True if SPTP power collapse is enabled on a5xx */

	bool sptp_pc_enabled;

	struct kgsl_memdesc *profile_buffer;

	unsigned int profile_index;

	struct kgsl_memdesc *pwrup_reglist;

drivers/gpu/msm/adreno_a5xx.c

+23 −35
Original line number Diff line number Diff line
@@ -89,7 +89,15 @@ static void a530_efuse_leakage(struct adreno_device *adreno_dev) 


static void a5xx_platform_setup(struct adreno_device *adreno_dev)

{

	set_bit(ADRENO_LM_CTRL, &adreno_dev->pwrctrl_flag);

	adreno_dev->sptp_pc_enabled =

		ADRENO_FEATURE(adreno_dev, ADRENO_SPTP_PC);



	if (adreno_is_a540(adreno_dev))

		adreno_dev->throttling_enabled = true;



	adreno_dev->hwcg_enabled = true;

	adreno_dev->lm_enabled =

		ADRENO_FEATURE(adreno_dev, ADRENO_LM);



	/* Set the GPU busy counter to use for frequency scaling */

	adreno_dev->perfctr_pwr_lo = A5XX_RBBM_PERFCTR_RBBM_0_LO;
@@ -261,8 +269,7 @@ static bool a5xx_is_sptp_idle(struct adreno_device *adreno_dev) 
	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);



	/* If feature is not supported or enabled, no worry */

	if (!ADRENO_FEATURE(adreno_dev, ADRENO_SPTP_PC) ||

		!test_bit(ADRENO_SPTP_PC_CTRL, &adreno_dev->pwrctrl_flag))

	if (!adreno_dev->sptp_pc_enabled)

		return true;

	kgsl_regread(device, A5XX_GPMU_SP_PWR_CLK_STATUS, &reg);

	if (reg & BIT(20))
@@ -404,8 +411,7 @@ static void a5xx_regulator_disable(struct adreno_device *adreno_dev) 
		return;



	/* If feature is not supported or not enabled */

	if (!ADRENO_FEATURE(adreno_dev, ADRENO_SPTP_PC) ||

		!test_bit(ADRENO_SPTP_PC_CTRL, &adreno_dev->pwrctrl_flag)) {

	if (!adreno_dev->sptp_pc_enabled) {

		/* Set the default register values; set SW_COLLAPSE to 1 */

		kgsl_regwrite(device, A5XX_GPMU_SP_POWER_CNTL, 0x778001);

		/*
@@ -456,8 +462,7 @@ static void a5xx_enable_pc(struct adreno_device *adreno_dev) 
{

	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);



	if (!ADRENO_FEATURE(adreno_dev, ADRENO_SPTP_PC) ||

		!test_bit(ADRENO_SPTP_PC_CTRL, &adreno_dev->pwrctrl_flag))

	if (!adreno_dev->sptp_pc_enabled)

		return;



	kgsl_regwrite(device, A5XX_GPMU_PWR_COL_INTER_FRAME_CTRL, 0x0000007F);
@@ -701,7 +706,7 @@ void a5xx_hwcg_set(struct adreno_device *adreno_dev, bool on) 
	const struct adreno_a5xx_core *a5xx_core = to_a5xx_core(adreno_dev);

	int i;



	if (!test_bit(ADRENO_HWCG_CTRL, &adreno_dev->pwrctrl_flag))

	if (!adreno_dev->hwcg_enabled)

		return;



	for (i = 0; i < a5xx_core->hwcg_count; i++)
@@ -934,8 +939,7 @@ static void a530_lm_init(struct adreno_device *adreno_dev) 
	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);

	const struct adreno_a5xx_core *a5xx_core = to_a5xx_core(adreno_dev);



	if (!ADRENO_FEATURE(adreno_dev, ADRENO_LM) ||

		!test_bit(ADRENO_LM_CTRL, &adreno_dev->pwrctrl_flag))

	if (!adreno_dev->lm_enabled)

		return;



	/* If something was wrong with the sequence file, return */
@@ -985,8 +989,7 @@ static void a530_lm_enable(struct adreno_device *adreno_dev) 
{

	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);



	if (!ADRENO_FEATURE(adreno_dev, ADRENO_LM) ||

		!test_bit(ADRENO_LM_CTRL, &adreno_dev->pwrctrl_flag))

	if (!adreno_dev->lm_enabled)

		return;



	/* If no sequence properly initialized, return */
@@ -1015,10 +1018,10 @@ static void a540_lm_init(struct adreno_device *adreno_dev) 
		<< AGC_GPU_VERSION_SHIFT);

	unsigned int r;



	if (!test_bit(ADRENO_THROTTLING_CTRL, &adreno_dev->pwrctrl_flag))

	if (!adreno_dev->throttling_enabled)

		agc_lm_config |= AGC_THROTTLE_DISABLE;



	if (lm_on(adreno_dev)) {

	if (adreno_dev->lm_enabled) {

		agc_lm_config |=

			AGC_LM_CONFIG_ENABLE_GPMU_ADAPTIVE |

			AGC_LM_CONFIG_ISENSE_ENABLE;
@@ -1096,20 +1099,11 @@ static void a5xx_pwrlevel_change_settings(struct adreno_device *adreno_dev, 
				unsigned int prelevel, unsigned int postlevel,

				bool post)

{

	int on = 0;



	/* On pre A540 HW only call through if LMx is supported and enabled */

	if (ADRENO_FEATURE(adreno_dev, ADRENO_LM) &&

		test_bit(ADRENO_LM_CTRL, &adreno_dev->pwrctrl_flag))

		on = ADRENO_LM;



	/* On 540+ HW call through unconditionally as long as GPMU is enabled */

	if (ADRENO_FEATURE(adreno_dev, ADRENO_GPMU)) {

		if (adreno_is_a540(adreno_dev))

			on = ADRENO_GPMU;

	}



	if (!on)

	/*

	 * On pre A540 HW only call through if LMx is supported and enabled, and

	 * always call through for a540

	 */

	if (!adreno_is_a540(adreno_dev) && !adreno_dev->lm_enabled)

		return;



	if (!post) {
@@ -1158,13 +1152,7 @@ static int64_t a5xx_read_throttling_counters(struct adreno_device *adreno_dev) 
	uint32_t th[ADRENO_GPMU_THROTTLE_COUNTERS];

	struct adreno_busy_data *busy = &adreno_dev->busy_data;



	if (!adreno_is_a540(adreno_dev))

		return 0;



	if (!ADRENO_FEATURE(adreno_dev, ADRENO_GPMU))

		return 0;



	if (!test_bit(ADRENO_THROTTLING_CTRL, &adreno_dev->pwrctrl_flag))

	if (!adreno_dev->throttling_enabled)

		return 0;



	for (i = 0; i < ADRENO_GPMU_THROTTLE_COUNTERS; i++) {

drivers/gpu/msm/adreno_a5xx.h

+1 −7
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (c) 2015-2017,2019 The Linux Foundation. All rights reserved.

 * Copyright (c) 2015-2017,2019-2020 The Linux Foundation. All rights reserved.

 */



#ifndef _ADRENO_A5XX_H_
@@ -205,12 +205,6 @@ void a5xx_hwcg_set(struct adreno_device *adreno_dev, bool on); 
#define LM_DEFAULT_LIMIT		6000

#define A530_DEFAULT_LEAKAGE		0x004E001A



static inline bool lm_on(struct adreno_device *adreno_dev)

{

	return ADRENO_FEATURE(adreno_dev, ADRENO_LM) &&

		test_bit(ADRENO_LM_CTRL, &adreno_dev->pwrctrl_flag);

}



/**

 * to_a5xx_core - return the a5xx specific GPU core struct

 * @adreno_dev: An Adreno GPU device handle

drivers/gpu/msm/adreno_a6xx.c

+4 −3
Original line number Diff line number Diff line
@@ -238,7 +238,7 @@ static void a6xx_hwcg_set(struct adreno_device *adreno_dev, bool on) 
	unsigned int value;

	int i;



	if (!test_bit(ADRENO_HWCG_CTRL, &adreno_dev->pwrctrl_flag))

	if (!adreno_dev->hwcg_enabled)

		on = false;



	if (gmu_core_isenabled(device)) {
@@ -1021,8 +1021,7 @@ static int64_t a6xx_read_throttling_counters(struct adreno_device *adreno_dev) 
	u32 a, b, c;

	struct adreno_busy_data *busy = &adreno_dev->busy_data;



	if (!ADRENO_FEATURE(adreno_dev, ADRENO_LM) ||

			!test_bit(ADRENO_LM_CTRL, &adreno_dev->pwrctrl_flag))

	if (!adreno_dev->lm_enabled)

		return 0;



	/* The counters are selected in a6xx_gmu_enable_lm() */
@@ -2281,6 +2280,8 @@ static void a6xx_platform_setup(struct adreno_device *adreno_dev) 
{

	struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);



	adreno_dev->hwcg_enabled = true;



	adreno_dev->preempt.preempt_level = 1;

	adreno_dev->preempt.skipsaverestore = true;

	adreno_dev->preempt.usesgmem = true;