Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 25d4d341 authored Jul 13, 2015 by Andy Shevchenko Committed by Stephen Boyd Jul 28, 2015

clk: socfpga: switch to GENMASK()



Convert the code to use GENMASK() helper instead of div_mask() macro.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

parent 4b5fb7dc

drivers/clk/socfpga/clk-gate-a10.c

+1 −1

Original line number	Original line	Diff line number	Diff line
	@@ -39,7 +39,7 @@ static unsigned long socfpga_gate_clk_recalc_rate(struct clk_hw *hwclk,
	div = socfpgaclk->fixed_div;		div = socfpgaclk->fixed_div;
	else if (socfpgaclk->div_reg) {		else if (socfpgaclk->div_reg) {
	val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;		val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
	val &= div_mask(socfpgaclk->width);		val &= GENMASK(socfpgaclk->width - 1, 0);
	div = (1 << val);		div = (1 << val);
	}		}

drivers/clk/socfpga/clk-gate.c

+1 −1

Original line number	Original line	Diff line number	Diff line
	@@ -105,7 +105,7 @@ static unsigned long socfpga_clk_recalc_rate(struct clk_hw *hwclk,
	div = socfpgaclk->fixed_div;		div = socfpgaclk->fixed_div;
	else if (socfpgaclk->div_reg) {		else if (socfpgaclk->div_reg) {
	val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;		val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
	val &= div_mask(socfpgaclk->width);		val &= GENMASK(socfpgaclk->width - 1, 0);
	/* Check for GPIO_DB_CLK by its offset */		/* Check for GPIO_DB_CLK by its offset */
	if ((int) socfpgaclk->div_reg & SOCFPGA_GPIO_DB_CLK_OFFSET)		if ((int) socfpgaclk->div_reg & SOCFPGA_GPIO_DB_CLK_OFFSET)
	div = val + 1;		div = val + 1;

drivers/clk/socfpga/clk-periph-a10.c

+1 −1

Original line number	Original line	Diff line number	Diff line
	@@ -38,7 +38,7 @@ static unsigned long clk_periclk_recalc_rate(struct clk_hw *hwclk,
	div = socfpgaclk->fixed_div;		div = socfpgaclk->fixed_div;
	} else if (socfpgaclk->div_reg) {		} else if (socfpgaclk->div_reg) {
	div = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;		div = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
	div &= div_mask(socfpgaclk->width);		div &= GENMASK(socfpgaclk->width - 1, 0);
	div += 1;		div += 1;
	} else {		} else {
	div = ((readl(socfpgaclk->hw.reg) & 0x7ff) + 1);		div = ((readl(socfpgaclk->hw.reg) & 0x7ff) + 1);

drivers/clk/socfpga/clk-periph.c

+1 −1

Original line number	Original line	Diff line number	Diff line
	@@ -35,7 +35,7 @@ static unsigned long clk_periclk_recalc_rate(struct clk_hw *hwclk,
	} else {		} else {
	if (socfpgaclk->div_reg) {		if (socfpgaclk->div_reg) {
	val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;		val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
	val &= div_mask(socfpgaclk->width);		val &= GENMASK(socfpgaclk->width - 1, 0);
	parent_rate /= (val + 1);		parent_rate /= (val + 1);
	}		}
	div = ((readl(socfpgaclk->hw.reg) & 0x1ff) + 1);		div = ((readl(socfpgaclk->hw.reg) & 0x1ff) + 1);

drivers/clk/socfpga/clk.h

+0 −1

Original line number	Original line	Diff line number	Diff line
	@@ -26,7 +26,6 @@
	#define CLKMGR_PERPLL_SRC 0xAC		#define CLKMGR_PERPLL_SRC 0xAC

	#define SOCFPGA_MAX_PARENTS 5		#define SOCFPGA_MAX_PARENTS 5
	#define div_mask(width) ((1 << (width)) - 1)

	#define streq(a, b) (strcmp((a), (b)) == 0)		#define streq(a, b) (strcmp((a), (b)) == 0)
	#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \		#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \