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Commit 258bac4a authored by Chaotian Jing's avatar Chaotian Jing Committed by Ulf Hansson
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mmc: mediatek: add bus_clk control 



when gate MSDC0_HCLK, access register will hang, even the MSDC driver
will never accessing register after HCLK was gated, but for safety, need
gate the bus_clk(which used to access register) too.

Signed-off-by: default avatarChaotian Jing <chaotian.jing@mediatek.com>
Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
parent 716b717a

drivers/mmc/host/mtk-sd.c

+6 −0
Original line number Diff line number Diff line
@@ -387,6 +387,7 @@ struct msdc_host { 


	struct clk *src_clk;	/* msdc source clock */

	struct clk *h_clk;      /* msdc h_clk */

	struct clk *bus_clk;	/* bus clock which used to access register */

	struct clk *src_clk_cg; /* msdc source clock control gate */

	u32 mclk;		/* mmc subsystem clock frequency */

	u32 src_clk_freq;	/* source clock frequency */
@@ -660,12 +661,14 @@ static void msdc_gate_clock(struct msdc_host *host) 
{

	clk_disable_unprepare(host->src_clk_cg);

	clk_disable_unprepare(host->src_clk);

	clk_disable_unprepare(host->bus_clk);

	clk_disable_unprepare(host->h_clk);

}



static void msdc_ungate_clock(struct msdc_host *host)

{

	clk_prepare_enable(host->h_clk);

	clk_prepare_enable(host->bus_clk);

	clk_prepare_enable(host->src_clk);

	clk_prepare_enable(host->src_clk_cg);

	while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB))
@@ -1900,6 +1903,9 @@ static int msdc_drv_probe(struct platform_device *pdev) 
		goto host_free;

	}



	host->bus_clk = devm_clk_get(&pdev->dev, "bus_clk");

	if (IS_ERR(host->bus_clk))

		host->bus_clk = NULL;

	/*source clock control gate is optional clock*/

	host->src_clk_cg = devm_clk_get(&pdev->dev, "source_cg");

	if (IS_ERR(host->src_clk_cg))