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Commit 716b717a authored by Chaotian Jing's avatar Chaotian Jing Committed by Ulf Hansson
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mmc: dt-bindings: add "bus-clk" for MT2712 



On MT2712 MSDC0/3, HCLK/bus-clk need gate/ungate together,
or will hang when access MSDC register.

Signed-off-by: default avatarChaotian Jing <chaotian.jing@mediatek.com>
Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
parent 32b64b03

Documentation/devicetree/bindings/mmc/mtk-sd.txt

+1 −0
Original line number Diff line number Diff line
@@ -22,6 +22,7 @@ Required properties: 
	"source" - source clock (required)

	"hclk" - HCLK which used for host (required)

	"source_cg" - independent source clock gate (required for MT2712)

	"bus_clk" - bus clock used for internal register access (required for MT2712 MSDC0/3)

- pinctrl-names: should be "default", "state_uhs"

- pinctrl-0: should contain default/high speed pin ctrl

- pinctrl-1: should contain uhs mode pin ctrl