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Commit 24a61b2a authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Add support for UART console on sdxlemur target"

parents 92b80c91 fd2cdba9

qcom/sdxlemur-pinctrl.dtsi

+26 −0
Original line number Diff line number Diff line
@@ -12,5 +12,31 @@ 
		interrupt-controller;

		interrupt-parent = <&intc>;

		#interrupt-cells = <2>;



		uart3_console_active: uart3_console_active {

			mux {

				pins = "gpio8", "gpio9";

				function = "blsp_uart3";

			};



			config {

				pins = "gpio8", "gpio9";

				drive-strength = <2>;

				bias-disable;

				};

			};



		uart3_console_sleep: uart3_console_sleep {

			mux {

				pins = "gpio8", "gpio9";

				function = "blsp_uart3";

			};



			config {

				pins = "gpio8", "gpio9";

				drive-strength = <2>;

				bias-disable;

			};

		};

	};

};

qcom/sdxlemur.dtsi

+13 −0
Original line number Diff line number Diff line
@@ -248,6 +248,19 @@ 
		#reset-cells = <1>;

	};



	serial_uart: serial@831000 {

		compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";

		reg = <0x831000 0x200>;

		interrupts = <0 26 0>;

		clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,

			 <&gcc GCC_BLSP1_AHB_CLK>;

		clock-names = "core", "iface";

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&uart3_console_active>;

		pinctrl-1 = <&uart3_console_sleep>;

		status = "ok";

	};



	apsscc: clock-controller@17808000 {

		compatible = "qcom,dummycc";

		clock-output-names = "apsscc_clocks";