Merge "ARM: dts: msm: Add support for ddr scaling on sdxlemur"

* ARM Performance Monitor Units

ARM cores often have a PMU for counting cpu and cache events like cache misses

and hits. The interface to the PMU is part of the ARM ARM. The ARM PMU

representation in the device tree should be done as under:-

Required properties:

- compatible : should be one of

	"apm,potenza-pmu"

	"arm,armv8-pmuv3"

	"arm,cortex-a73-pmu"

	"arm,cortex-a72-pmu"

	"arm,cortex-a57-pmu"

	"arm,cortex-a53-pmu"

	"arm,cortex-a35-pmu"

	"arm,cortex-a17-pmu"

	"arm,cortex-a15-pmu"

	"arm,cortex-a12-pmu"

	"arm,cortex-a9-pmu"

	"arm,cortex-a8-pmu"

	"arm,cortex-a7-pmu"

	"arm,cortex-a5-pmu"

	"arm,arm11mpcore-pmu"

	"arm,arm1176-pmu"

	"arm,arm1136-pmu"

	"brcm,vulcan-pmu"

	"cavium,thunder-pmu"

	"qcom,scorpion-pmu"

	"qcom,scorpion-mp-pmu"

	"qcom,krait-pmu"

- interrupts : 1 combined interrupt or 1 per core. If the interrupt is a per-cpu

               interrupt (PPI) then 1 interrupt should be specified.

Optional properties:

- interrupt-affinity : When using SPIs, specifies a list of phandles to CPU

                       nodes corresponding directly to the affinity of

		       the SPIs listed in the interrupts property.

                       When using a PPI, specifies a list of phandles to CPU

		       nodes corresponding to the set of CPUs which have

		       a PMU of this type signalling the PPI listed in the

		       interrupts property, unless this is already specified

		       by the PPI interrupt specifier itself (in which case

		       the interrupt-affinity property shouldn't be present).

                       This property should be present when there is more than

		       a single SPI.

- qcom,no-pc-write : Indicates that this PMU doesn't support the 0xc and 0xd

                     events.

- secure-reg-access : Indicates that the ARMv7 Secure Debug Enable Register

		      (SDER) is accessible. This will cause the driver to do

		      any setup required that is only possible in ARMv7 secure

		      state. If not present the ARMv7 SDER will not be touched,

		      which means the PMU may fail to operate unless external

		      code (bootloader or security monitor) has performed the

		      appropriate initialisation. Note that this property is

		      not valid for non-ARMv7 CPUs or ARMv7 CPUs booting Linux

		      in Non-secure state.

Example:

pmu {

        compatible = "arm,cortex-a9-pmu";

        interrupts = <100 101>;

};

#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>

#include <dt-bindings/spmi/spmi.h>

#define MHZ_TO_MBPS(mhz, w) ((mhz * 1000000 * w) / (1024 * 1024))

#define BW_OPP_ENTRY(mhz, w) opp-mhz {opp-hz = /bits/ 64 <MHZ_TO_MBPS(mhz, w)>;}

/ {

	#address-cells = <1>;

	#size-cells = <1>;

		};

	};

	cpu_pmu: cpu-pmu {

		compatible = "arm,cortex-a7-pmu";

		interrupts = <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>;

	};

	qcom,msm-imem@1468f000 {

		compatible = "qcom,msm-imem";

		reg = <0x1468f000 0x1000>; /* Address and size of IMEM */

		status = "disabled";

	};

	ddr_bw_opp_table: ddr-bw-opp-table {

		compatible = "operating-points-v2";

		BW_OPP_ENTRY(  100, 4); /*   381 MB/s */

		BW_OPP_ENTRY(  200, 4); /*   762 MB/s */

		BW_OPP_ENTRY(  300, 4); /*  1144 MB/s */

		BW_OPP_ENTRY(  451, 4); /*  1720 MB/s */

		BW_OPP_ENTRY(  547, 4); /*  2086 MB/s */

		BW_OPP_ENTRY(  681, 4); /*  2597 MB/s */

		BW_OPP_ENTRY(  768, 4); /*  2929 MB/s */

		BW_OPP_ENTRY( 1017, 4); /*  3879 MB/s */

		BW_OPP_ENTRY( 1353, 4); /*  5161 MB/s */

		BW_OPP_ENTRY( 1555, 4); /*  5931 MB/s */

		BW_OPP_ENTRY( 1804, 4); /*  6881 MB/s */

		BW_OPP_ENTRY( 2092, 4); /*  7980 MB/s */

	};

	cpu0_cpu_ddr_lat: qcom,cpu0-cpu-ddr-lat {

		compatible = "qcom,devfreq-icc";

		governor = "compute";

		interconnects = <&mem_noc MASTER_APPSS_PROC &mc_virt SLAVE_EBI1>;

		qcom,active-only;

		operating-points-v2 = <&ddr_bw_opp_table>;

	};

	cpu0_cpu_ddr_tbl: qcom,cpu0-cpu-ddr-tbl {

		qcom,core-dev-table =

			<   345600  MHZ_TO_MBPS( 300, 4) >,

			<   576000  MHZ_TO_MBPS( 768, 4) >,

			<  1440000  MHZ_TO_MBPS(1555, 4) >,

			<  1497600  MHZ_TO_MBPS(2092, 4) >;

	};

	memlat_cpugrp: qcom,memlat-cpugrp {

		compatible = "qcom,arm-memlat-cpugrp";

		qcom,cpulist = <&CPU0>;

		cpu0_cpu_ddr_latmon: qcom,cpu0-cpu-ddr-latmon {

			compatible = "qcom,arm-compute-mon";

			qcom,cpulist = <&CPU0>;

			qcom,target-dev = <&cpu0_cpu_ddr_lat>;

			qcom,core-dev-table = <&cpu0_cpu_ddr_tbl>;

		};

	};

	sdhc_1: sdhci@8804000 {

		compatible = "qcom,sdhci-msm-v5";

		reg = <0x08804000 0x1000>;