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Commit 5d0dac9f authored by Rishabh Bhatnagar's avatar Rishabh Bhatnagar
Browse files

ARM: dts: msm: Add support for ddr scaling on sdxlemur 

Add ddr bandwidth table and other dt nodes to support ddr
bandwidth scaling for sdxlemur target.

Change-Id: I9580bd0bb7d78019b2750a2bb7f8df273560dce0
parent 043c3d60

qcom/sdxlemur.dtsi

+47 −0
Original line number Original line Diff line number Diff line
@@ -10,6 +10,9 @@ 
#include <dt-bindings/soc/qcom,rpmh-rsc.h>

#include <dt-bindings/soc/qcom,rpmh-rsc.h>

#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>

#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>





#define MHZ_TO_MBPS(mhz, w) ((mhz * 1000000 * w) / (1024 * 1024))

#define BW_OPP_ENTRY(mhz, w) opp-mhz {opp-hz = /bits/ 64 <MHZ_TO_MBPS(mhz, w)>;}



/ {

/ {

	#address-cells = <1>;

	#address-cells = <1>;

	#size-cells = <1>;

	#size-cells = <1>;
@@ -437,6 +440,50 @@ 
		status = "disabled";

		status = "disabled";

	};

	};





	ddr_bw_opp_table: ddr-bw-opp-table {

		compatible = "operating-points-v2";

		BW_OPP_ENTRY(  100, 4); /*   381 MB/s */

		BW_OPP_ENTRY(  200, 4); /*   762 MB/s */

		BW_OPP_ENTRY(  300, 4); /*  1144 MB/s */

		BW_OPP_ENTRY(  451, 4); /*  1720 MB/s */

		BW_OPP_ENTRY(  547, 4); /*  2086 MB/s */

		BW_OPP_ENTRY(  681, 4); /*  2597 MB/s */

		BW_OPP_ENTRY(  768, 4); /*  2929 MB/s */

		BW_OPP_ENTRY( 1017, 4); /*  3879 MB/s */

		BW_OPP_ENTRY( 1353, 4); /*  5161 MB/s */

		BW_OPP_ENTRY( 1555, 4); /*  5931 MB/s */

		BW_OPP_ENTRY( 1804, 4); /*  6881 MB/s */

		BW_OPP_ENTRY( 2092, 4); /*  7980 MB/s */

	};



	cpu0_cpu_ddr_lat: qcom,cpu0-cpu-ddr-lat {

		compatible = "qcom,devfreq-icc";

		governor = "compute";

		interconnects = <&mem_noc MASTER_APPSS_PROC &mc_virt SLAVE_EBI1>;

		qcom,active-only;

		operating-points-v2 = <&ddr_bw_opp_table>;

	};



	cpu0_cpu_ddr_tbl: qcom,cpu0-cpu-ddr-tbl {

		qcom,core-dev-table =

			<   345600  MHZ_TO_MBPS( 300, 4) >,

			<   576000  MHZ_TO_MBPS( 768, 4) >,

			<  1440000  MHZ_TO_MBPS(1555, 4) >,

			<  1497600  MHZ_TO_MBPS(2092, 4) >;

	};



	memlat_cpugrp: qcom,memlat-cpugrp {

		compatible = "qcom,arm-memlat-cpugrp";

		qcom,cpulist = <&CPU0>;



		cpu0_cpu_ddr_latmon: qcom,cpu0-cpu-ddr-latmon {

			compatible = "qcom,arm-compute-mon";

			qcom,cpulist = <&CPU0>;

			qcom,target-dev = <&cpu0_cpu_ddr_lat>;

			qcom,core-dev-table = <&cpu0_cpu_ddr_tbl>;

		};

	};



	sdhc_1: sdhci@8804000 {

	sdhc_1: sdhci@8804000 {

		compatible = "qcom,sdhci-msm-v5";

		compatible = "qcom,sdhci-msm-v5";

		reg = <0x08804000 0x1000>;

		reg = <0x08804000 0x1000>;