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Commit 1fa04d92 authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'imx-dt64-4.8' of... 

Merge tag 'imx-dt64-4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt64

The Freescale arm64 device tree updates for 4.8:
 - Update address-cells and reg properties of cpu nodes, considering
   MPIDR_EL1[63:32] bits are not used for CPUs identification on ls1043a
   and ls2080a
 - Adds the cache nodes and next-level-cache property for ls1043a and
   ls2080a to get cacheinfo work on these platforms
 - Add dma-coherent for ls1043a PCI nodes to utilize the hardware
   capability on data coherency
 - Add dis_rxdet_inp3_quirk property for USB3 device to disable rx
   detection in P3 PHY mode

* tag 'imx-dt64-4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux

:
  arm64: dts: ls2080a: Add cache nodes for cacheinfo support
  arm64: dts: ls1043a: Add cache nodes for cacheinfo support
  arm64: dts: ls1043a: Add 'dma-coherent' for ls1043a PCI nodes
  bindings: PCI: layerscape: Add 'dma-coherent' property
  arm64: dts: ls1043a: Add dis_rxdet_inp3_quirk property to USB3 node
  arm64: dts: ls2080a: Add dis_rxdet_inp3_quirk property to USB3 node
  arm64: dts: fsl: Update address-cells and reg properties of cpu nodes

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 87040f7c 2983e625

Documentation/devicetree/bindings/pci/layerscape-pci.txt

+4 −0
Original line number Diff line number Diff line
@@ -24,6 +24,9 @@ Required properties: 
  The first entry must be a link to the SCFG device node

  The second entry must be '0' or '1' based on physical PCIe controller index.

  This is used to get SCFG PEXN registers

- dma-coherent: Indicates that the hardware IP block can ensure the coherency

  of the data transferred from/to the IP block. This can avoid the software

  cache flush/invalid actions, and improve the performance significantly.



Example:
@@ -38,6 +41,7 @@ Example: 
		#address-cells = <3>;

		#size-cells = <2>;

		device_type = "pci";

		dma-coherent;

		num-lanes = <4>;

		bus-range = <0x0 0xff>;

		ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */

arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi

+19 −5
Original line number Diff line number Diff line
@@ -51,7 +51,7 @@ 
	#size-cells = <2>;



	cpus {

		#address-cells = <2>;

		#address-cells = <1>;

		#size-cells = <0>;



		/*
@@ -63,29 +63,37 @@ 
		cpu0: cpu@0 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x0 0x0>;

			reg = <0x0>;

			clocks = <&clockgen 1 0>;

			next-level-cache = <&l2>;

		};



		cpu1: cpu@1 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x0 0x1>;

			reg = <0x1>;

			clocks = <&clockgen 1 0>;

			next-level-cache = <&l2>;

		};



		cpu2: cpu@2 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x0 0x2>;

			reg = <0x2>;

			clocks = <&clockgen 1 0>;

			next-level-cache = <&l2>;

		};



		cpu3: cpu@3 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x0 0x3>;

			reg = <0x3>;

			clocks = <&clockgen 1 0>;

			next-level-cache = <&l2>;

		};



		l2: l2-cache {

			compatible = "cache";

		};

	};
@@ -422,6 +430,7 @@ 
			interrupts = <0 60 0x4>;

			dr_mode = "host";

			snps,quirk-frame-length-adjustment = <0x20>;

			snps,dis_rxdet_inp3_quirk;

		};



		usb1: usb3@3000000 {
@@ -430,6 +439,7 @@ 
			interrupts = <0 61 0x4>;

			dr_mode = "host";

			snps,quirk-frame-length-adjustment = <0x20>;

			snps,dis_rxdet_inp3_quirk;

		};



		usb2: usb3@3100000 {
@@ -438,6 +448,7 @@ 
			interrupts = <0 63 0x4>;

			dr_mode = "host";

			snps,quirk-frame-length-adjustment = <0x20>;

			snps,dis_rxdet_inp3_quirk;

		};



		sata: sata@3200000 {
@@ -479,6 +490,7 @@ 
			#address-cells = <3>;

			#size-cells = <2>;

			device_type = "pci";

			dma-coherent;

			num-lanes = <4>;

			bus-range = <0x0 0xff>;

			ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */
@@ -503,6 +515,7 @@ 
			#address-cells = <3>;

			#size-cells = <2>;

			device_type = "pci";

			dma-coherent;

			num-lanes = <2>;

			bus-range = <0x0 0xff>;

			ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000   /* downstream I/O */
@@ -527,6 +540,7 @@ 
			#address-cells = <3>;

			#size-cells = <2>;

			device_type = "pci";

			dma-coherent;

			num-lanes = <2>;

			bus-range = <0x0 0xff>;

			ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000   /* downstream I/O */

arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi

+35 −9
Original line number Diff line number Diff line
@@ -51,7 +51,7 @@ 
	#size-cells = <2>;



	cpus {

		#address-cells = <2>;

		#address-cells = <1>;

		#size-cells = <0>;



		/*
@@ -65,57 +65,81 @@ 
		cpu@0 {

			device_type = "cpu";

			compatible = "arm,cortex-a57";

			reg = <0x0 0x0>;

			reg = <0x0>;

			clocks = <&clockgen 1 0>;

			next-level-cache = <&cluster0_l2>;

		};



		cpu@1 {

			device_type = "cpu";

			compatible = "arm,cortex-a57";

			reg = <0x0 0x1>;

			reg = <0x1>;

			clocks = <&clockgen 1 0>;

			next-level-cache = <&cluster0_l2>;

		};



		cpu@100 {

			device_type = "cpu";

			compatible = "arm,cortex-a57";

			reg = <0x0 0x100>;

			reg = <0x100>;

			clocks = <&clockgen 1 1>;

			next-level-cache = <&cluster1_l2>;

		};



		cpu@101 {

			device_type = "cpu";

			compatible = "arm,cortex-a57";

			reg = <0x0 0x101>;

			reg = <0x101>;

			clocks = <&clockgen 1 1>;

			next-level-cache = <&cluster1_l2>;

		};



		cpu@200 {

			device_type = "cpu";

			compatible = "arm,cortex-a57";

			reg = <0x0 0x200>;

			reg = <0x200>;

			clocks = <&clockgen 1 2>;

			next-level-cache = <&cluster2_l2>;

		};



		cpu@201 {

			device_type = "cpu";

			compatible = "arm,cortex-a57";

			reg = <0x0 0x201>;

			reg = <0x201>;

			clocks = <&clockgen 1 2>;

			next-level-cache = <&cluster2_l2>;

		};



		cpu@300 {

			device_type = "cpu";

			compatible = "arm,cortex-a57";

			reg = <0x0 0x300>;

			reg = <0x300>;

			clocks = <&clockgen 1 3>;

			next-level-cache = <&cluster3_l2>;

		};



		cpu@301 {

			device_type = "cpu";

			compatible = "arm,cortex-a57";

			reg = <0x0 0x301>;

			reg = <0x301>;

			clocks = <&clockgen 1 3>;

			next-level-cache = <&cluster3_l2>;

		};



		cluster0_l2: l2-cache0 {

			compatible = "cache";

		};



		cluster1_l2: l2-cache1 {

			compatible = "cache";

		};



		cluster2_l2: l2-cache2 {

			compatible = "cache";

		};



		cluster3_l2: l2-cache3 {

			compatible = "cache";

		};

	};
@@ -672,6 +696,7 @@ 
			interrupts = <0 80 0x4>; /* Level high type */

			dr_mode = "host";

			snps,quirk-frame-length-adjustment = <0x20>;

			snps,dis_rxdet_inp3_quirk;

		};



		usb1: usb3@3110000 {
@@ -681,6 +706,7 @@ 
			interrupts = <0 81 0x4>; /* Level high type */

			dr_mode = "host";

			snps,quirk-frame-length-adjustment = <0x20>;

			snps,dis_rxdet_inp3_quirk;

		};



		ccn@4000000 {