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Commit 2983e625 authored by Li Yang's avatar Li Yang Committed by Shawn Guo
Browse files

arm64: dts: ls2080a: Add cache nodes for cacheinfo support 



Adds the cache nodes and next-level-cache property for the
cacheinfo to work.

Signed-off-by: default avatarLi Yang <leoyang.li@nxp.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent ec049f33

arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi

+24 −0
Original line number Diff line number Diff line
@@ -67,6 +67,7 @@ 
			compatible = "arm,cortex-a57";

			reg = <0x0>;

			clocks = <&clockgen 1 0>;

			next-level-cache = <&cluster0_l2>;

		};



		cpu@1 {
@@ -74,6 +75,7 @@ 
			compatible = "arm,cortex-a57";

			reg = <0x1>;

			clocks = <&clockgen 1 0>;

			next-level-cache = <&cluster0_l2>;

		};



		cpu@100 {
@@ -81,6 +83,7 @@ 
			compatible = "arm,cortex-a57";

			reg = <0x100>;

			clocks = <&clockgen 1 1>;

			next-level-cache = <&cluster1_l2>;

		};



		cpu@101 {
@@ -88,6 +91,7 @@ 
			compatible = "arm,cortex-a57";

			reg = <0x101>;

			clocks = <&clockgen 1 1>;

			next-level-cache = <&cluster1_l2>;

		};



		cpu@200 {
@@ -95,6 +99,7 @@ 
			compatible = "arm,cortex-a57";

			reg = <0x200>;

			clocks = <&clockgen 1 2>;

			next-level-cache = <&cluster2_l2>;

		};



		cpu@201 {
@@ -102,6 +107,7 @@ 
			compatible = "arm,cortex-a57";

			reg = <0x201>;

			clocks = <&clockgen 1 2>;

			next-level-cache = <&cluster2_l2>;

		};



		cpu@300 {
@@ -109,6 +115,7 @@ 
			compatible = "arm,cortex-a57";

			reg = <0x300>;

			clocks = <&clockgen 1 3>;

			next-level-cache = <&cluster3_l2>;

		};



		cpu@301 {
@@ -116,6 +123,23 @@ 
			compatible = "arm,cortex-a57";

			reg = <0x301>;

			clocks = <&clockgen 1 3>;

			next-level-cache = <&cluster3_l2>;

		};



		cluster0_l2: l2-cache0 {

			compatible = "cache";

		};



		cluster1_l2: l2-cache1 {

			compatible = "cache";

		};



		cluster2_l2: l2-cache2 {

			compatible = "cache";

		};



		cluster3_l2: l2-cache3 {

			compatible = "cache";

		};

	};