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Commit 1e5d716c authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Add USB CSR clock entry on Lahaina"

parents 2b616db3 b92c3f5e

bindings/usb/qcom,dwc3.txt

+3 −0
Original line number Diff line number Diff line
@@ -23,6 +23,9 @@ Optional clocks: 
			Not present on "qcom,msm8996-dwc3" compatible.

  "cfg_noc"		System Config NOC clock.

			Not present on "qcom,msm8996-dwc3" compatible.

  "core_csr"		Allows to set/clear FORCE_MEM_CORE_ON with USB core

                        clock to retain USB controller CSR across system deep

			sleep.

- assigned-clocks:	Should be:

				MOCK_UTMI_CLK

				MASTER_CLK

qcom/lahaina-usb.dtsi

+6 −4
Original line number Diff line number Diff line
@@ -29,9 +29,10 @@ 
			<&clock_gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,

			<&clock_gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,

			<&clock_gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,

			<&clock_gcc GCC_USB30_PRIM_SLEEP_CLK>;

			<&clock_gcc GCC_USB30_PRIM_SLEEP_CLK>,

			<&clock_gcc GCC_USB30_PRIM_MASTER_CLK__FORCE_MEM_CORE_ON>;

		clock-names = "core_clk", "iface_clk", "bus_aggr_clk",

					"utmi_clk", "sleep_clk";

				"utmi_clk", "sleep_clk", "core_csr_clk";



		resets = <&clock_gcc GCC_USB30_PRIM_BCR>;

		reset-names = "core_reset";
@@ -355,9 +356,10 @@ 
			<&clock_gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,

			<&clock_gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,

			<&clock_gcc GCC_USB30_SEC_SLEEP_CLK>,

			<&clock_gcc GCC_USB3_SEC_CLKREF_EN>;

			<&clock_gcc GCC_USB3_SEC_CLKREF_EN>,

			<&clock_gcc GCC_USB30_SEC_MASTER_CLK__FORCE_MEM_CORE_ON>;

		clock-names = "core_clk", "iface_clk", "bus_aggr_clk",

					"utmi_clk", "sleep_clk", "xo";

			"utmi_clk", "sleep_clk", "xo", "core_csr_clk";



		resets = <&clock_gcc GCC_USB30_SEC_BCR>;

		reset-names = "core_reset";