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Commit b92c3f5e authored by Mayank Rana's avatar Mayank Rana
Browse files

ARM: dts: msm: Add USB CSR clock entry on Lahaina 

USB CSR clock is required to keep ON for retaining USB controller
CSR while going into CXPC. Hence add USB CSR clock entries with
primary and secondary USB controller to support USB host mode bus
suspend usecase.

Change-Id: I1fe6dbedbb434a546fd719232411d37902b88f70
parent fb37edde

qcom/lahaina-usb.dtsi

+6 −4
Original line number Diff line number Diff line
@@ -29,9 +29,10 @@ 
			<&clock_gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,

			<&clock_gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,

			<&clock_gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,

			<&clock_gcc GCC_USB30_PRIM_SLEEP_CLK>;

			<&clock_gcc GCC_USB30_PRIM_SLEEP_CLK>,

			<&clock_gcc GCC_USB30_PRIM_MASTER_CLK__FORCE_MEM_CORE_ON>;

		clock-names = "core_clk", "iface_clk", "bus_aggr_clk",

					"utmi_clk", "sleep_clk";

				"utmi_clk", "sleep_clk", "core_csr_clk";



		resets = <&clock_gcc GCC_USB30_PRIM_BCR>;

		reset-names = "core_reset";
@@ -355,9 +356,10 @@ 
			<&clock_gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,

			<&clock_gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,

			<&clock_gcc GCC_USB30_SEC_SLEEP_CLK>,

			<&clock_gcc GCC_USB3_SEC_CLKREF_EN>;

			<&clock_gcc GCC_USB3_SEC_CLKREF_EN>,

			<&clock_gcc GCC_USB30_SEC_MASTER_CLK__FORCE_MEM_CORE_ON>;

		clock-names = "core_clk", "iface_clk", "bus_aggr_clk",

					"utmi_clk", "sleep_clk", "xo";

			"utmi_clk", "sleep_clk", "xo", "core_csr_clk";



		resets = <&clock_gcc GCC_USB30_SEC_BCR>;

		reset-names = "core_reset";