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Commit 1ddc5d94 authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'net-ethernet-mediatek-convert-to-PHYLINK' 



René van Dorst says:

====================
net: ethernet: mediatek: convert to PHYLINK

These patches converts mediatek driver to PHYLINK API.

v3->v4:
* Phylink improvements and clean-ups after review
v2->v3:
* Phylink improvements and clean-ups after review
v1->v2:
* Rebase for mt76x8 changes
* Phylink improvements and clean-ups after review
* SGMII port doesn't support 2.5Gbit in SGMII mode only in BASE-X mode.
  Refactor the code.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents cb6ec975 bd69baaa

Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt

+0 −2
Original line number Diff line number Diff line
@@ -9,8 +9,6 @@ Required Properties: 
	- "mediatek,mt7622-sgmiisys", "syscon"

	- "mediatek,mt7629-sgmiisys", "syscon"

- #clock-cells: Must be 1

- mediatek,physpeed: Should be one of "auto", "1000" or "2500" to match up

		     the capability of the target PHY.



The SGMIISYS controller uses the common clk binding from

Documentation/devicetree/bindings/clock/clock-bindings.txt

arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts

+19 −9
Original line number Diff line number Diff line
@@ -115,24 +115,34 @@ 
};



&eth {

	pinctrl-names = "default";

	pinctrl-0 = <&eth_pins>;

	status = "okay";

	gmac0: mac@0 {

		compatible = "mediatek,eth-mac";

		reg = <0>;

		phy-mode = "2500base-x";



		fixed-link {

			speed = <2500>;

			full-duplex;

			pause;

		};

	};



	gmac1: mac@1 {

		compatible = "mediatek,eth-mac";

		reg = <1>;

		phy-handle = <&phy5>;

		phy-mode = "rgmii";



		fixed-link {

			speed = <1000>;

			full-duplex;

			pause;

		};

	};



	mdio-bus {

	mdio: mdio-bus {

		#address-cells = <1>;

		#size-cells = <0>;



		phy5: ethernet-phy@5 {

			reg = <5>;

			phy-mode = "sgmii";

		};

	};

};

arch/arm64/boot/dts/mediatek/mt7622.dtsi

+0 −1
Original line number Diff line number Diff line
@@ -931,6 +931,5 @@ 
			     "syscon";

		reg = <0 0x1b128000 0 0x3000>;

		#clock-cells = <1>;

		mediatek,physpeed = "2500";

	};

};

drivers/net/ethernet/mediatek/Kconfig

+1 −1
Original line number Diff line number Diff line
@@ -9,7 +9,7 @@ if NET_VENDOR_MEDIATEK 


config NET_MEDIATEK_SOC

	tristate "MediaTek SoC Gigabit Ethernet support"

	select PHYLIB

	select PHYLINK

	---help---

	  This driver supports the gigabit ethernet MACs in the

	  MediaTek SoC family.

drivers/net/ethernet/mediatek/mtk_eth_path.c

+4 −71
Original line number Diff line number Diff line
@@ -239,10 +239,9 @@ static int mtk_eth_mux_setup(struct mtk_eth *eth, int path) 
	return err;

}



static int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id)

int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id)

{

	unsigned int val = 0;

	int sid, err, path;

	int err, path;



	path = (mac_id == 0) ?  MTK_ETH_PATH_GMAC1_SGMII :

				MTK_ETH_PATH_GMAC2_SGMII;
@@ -252,33 +251,10 @@ static int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id) 
	if (err)

		return err;



	/* The path GMAC to SGMII will be enabled once the SGMIISYS is being

	 * setup done.

	 */

	regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);



	regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0,

			   SYSCFG0_SGMII_MASK, ~(u32)SYSCFG0_SGMII_MASK);



	/* Decide how GMAC and SGMIISYS be mapped */

	sid = (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII)) ? 0 : mac_id;



	/* Setup SGMIISYS with the determined property */

	if (MTK_HAS_FLAGS(eth->sgmii->flags[sid], MTK_SGMII_PHYSPEED_AN))

		err = mtk_sgmii_setup_mode_an(eth->sgmii, sid);

	else

		err = mtk_sgmii_setup_mode_force(eth->sgmii, sid);



	if (err)

		return err;



	regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0,

			   SYSCFG0_SGMII_MASK, val);



	return 0;

}



static int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id)

int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id)

{

	int err, path = 0;
@@ -296,7 +272,7 @@ static int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id) 
	return 0;

}



static int mtk_gmac_rgmii_path_setup(struct mtk_eth *eth, int mac_id)

int mtk_gmac_rgmii_path_setup(struct mtk_eth *eth, int mac_id)

{

	int err, path;
@@ -311,46 +287,3 @@ static int mtk_gmac_rgmii_path_setup(struct mtk_eth *eth, int mac_id) 
	return 0;

}

int mtk_setup_hw_path(struct mtk_eth *eth, int mac_id, int phymode)

{

	int err;



	/* No mux'ing for MT7628/88 */

	if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))

		return 0;



	switch (phymode) {

	case PHY_INTERFACE_MODE_TRGMII:

	case PHY_INTERFACE_MODE_RGMII_TXID:

	case PHY_INTERFACE_MODE_RGMII_RXID:

	case PHY_INTERFACE_MODE_RGMII_ID:

	case PHY_INTERFACE_MODE_RGMII:

	case PHY_INTERFACE_MODE_MII:

	case PHY_INTERFACE_MODE_REVMII:

	case PHY_INTERFACE_MODE_RMII:

		if (MTK_HAS_CAPS(eth->soc->caps, MTK_RGMII)) {

			err = mtk_gmac_rgmii_path_setup(eth, mac_id);

			if (err)

				return err;

		}

		break;

	case PHY_INTERFACE_MODE_SGMII:

		if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) {

			err = mtk_gmac_sgmii_path_setup(eth, mac_id);

			if (err)

				return err;

		}

		break;

	case PHY_INTERFACE_MODE_GMII:

		if (MTK_HAS_CAPS(eth->soc->caps, MTK_GEPHY)) {

			err = mtk_gmac_gephy_path_setup(eth, mac_id);

			if (err)

				return err;

		}

		break;

	default:

		break;

	}



	return 0;

}