Commit 196de71a authored Jul 10, 2015 by James Liao Committed by Stephen Boyd Jul 28, 2015

clk: mediatek: Fix calculation of PLL rate settings



Avoid u32 overflow when calculate post divider setting, and
increase the max post divider setting from 3 (/8) to 4 (/16).

Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

parent b3be457e

drivers/clk/mediatek/clk-pll.c

+2 −2

Original line number	Diff line number	Diff line
		@@ -144,9 +144,9 @@ static void mtk_pll_calc_values(struct mtk_clk_pll pll, u32 pcw, u32 *postdiv,
		if (freq > pll->data->fmax)
		freq = pll->data->fmax;

		for (val = 0; val < 4; val++) {
		for (val = 0; val < 5; val++) {
		*postdiv = 1 << val;
		if (freq * *postdiv >= fmin)
		if ((u64)freq * *postdiv >= fmin)
		break;
		}