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Commit b3be457e authored by James Liao's avatar James Liao Committed by Stephen Boyd
Browse files

clk: mediatek: Fix PLL registers setting flow 



Write postdiv and pcw settings at the same time for PLLs if postdiv
and pcw settings are on the same register.

This is need by PLLs such as MT8173 MMPLL and ARM*PLL.

Signed-off-by: default avatarJames Liao <jamesjj.liao@mediatek.com>
Acked-by: default avatarSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
parent 9783c0d9

drivers/clk/mediatek/clk-pll.c

+12 −9
Original line number Diff line number Diff line
@@ -90,20 +90,23 @@ static unsigned long __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin, 
static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw,

		int postdiv)

{

	u32 con1, pd, val;

	u32 con1, val;

	int pll_en;



	/* set postdiv */

	pd = readl(pll->pd_addr);

	pd &= ~(POSTDIV_MASK << pll->data->pd_shift);

	pd |= (ffs(postdiv) - 1) << pll->data->pd_shift;

	writel(pd, pll->pd_addr);



	pll_en = readl(pll->base_addr + REG_CON0) & CON0_BASE_EN;



	/* set pcw */

	/* set postdiv */

	val = readl(pll->pd_addr);

	val &= ~(POSTDIV_MASK << pll->data->pd_shift);

	val |= (ffs(postdiv) - 1) << pll->data->pd_shift;



	/* postdiv and pcw need to set at the same time if on same register */

	if (pll->pd_addr != pll->pcw_addr) {

		writel(val, pll->pd_addr);

		val = readl(pll->pcw_addr);

	}



	/* set pcw */

	val &= ~GENMASK(pll->data->pcw_shift + pll->data->pcwbits - 1,

			pll->data->pcw_shift);

	val |= pcw << pll->data->pcw_shift;