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Commit 16b23c19 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Add device tree node for GP2 clock driven led"

parents 2729edb5 abdc40c6

bindings/leds/leds-qcom-clk.txt

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Qualcomm Technologies, Inc. clock controller based PWM driver

-------------------------------------------------------------



Qualcomm Technologies, Inc. provides clock controller to be connected to LED

to generate PWM. This driver can configure duty-cycle of clock to get the

required brightness. The complete clock duty-cycle is 100 and brightness is

denoted by the period in which signal is active or high.



Required properties:

- compatible: Should be "qcom,clk-led-pwm".

- clock_names: Should be "core".

- clocks: Should contain the phandle of the source clock.

- assgined-clocks: Phandle of the source clock.

- assinged-clock-rates: Desired frequency of the source clock.

- qcom,max_duty: Maximum duty cycle that can be set on the clock.

		   Should be less than 100.

- pinctrl-names: Property should contain "active" and "sleep" for the

		   pin configurations during the usecase and during idle.

- pinctrl-x: phandle to the default/sleep pin configurations.



Optional properties:

- qcom,label: Label for the sysfs node.





Example:



qcom_clk_led {

	compatible = "qcom,clk-led-pwm";

	qcom,label = "led_clk_pwm";

	qcom,max_duty = <80>;

	clocks = <&clock_gcc GCC_GP2_CLK>;

	clock-names = "core";

	assigned-clocks = <&clock_gcc GCC_GP2_CLK>;

	assigned-clock-rates = <80000>;

	pinctrl-names = "active", "sleep";

	pinctrl-0 = <&qcom_clk_led_gp2_active>;

	pinctrl-1 = <&qcom_clk_led_gp2_sleep>;

};



== Pinctrl configurations ==

qcom_clk_led_gp2_pins: qcom_clk_led_gp2_pins {

	qcom_clk_led_gp2_active: qcom_clk_led_gp2_active {

		mux {

			pins = "gpio21";

			function = "gcc_gp2";

		};



		config {

			pins = "gpio21";

			drive-strength = <2>;

			bias-disable;

		};

	};



	qcom_clk_led_gp2_sleep: qqcom_clk_led_gp2_sleep {

		mux {

			pins = "gpio21";

			function = "gpio";

		};



		config {

			pins = "gpio21";

			drive-strength = <2>;

			bias-pull-down;

		};

	};

};

qcom/sm8150-pinctrl.dtsi

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@@ -5098,5 +5098,34 @@ 
				output-high;

			};

		};



		qcom_clk_led_gp2_pins: qcom_clk_led_gp2_pins {

			qcom_clk_led_gp2_active: qcom_clk_led_gp2_active {

				mux {

					pins = "gpio21";

					function = "gcc_gp2";

				};



				config {

					pins = "gpio21";

					drive-strength = <2>;

					bias-disable;

				};

			};



			qcom_clk_led_gp2_sleep: qqcom_clk_led_gp2_sleep {

				mux {

					pins = "gpio21";

					function = "gpio";

				};



				config {

					pins = "gpio21";

					drive-strength = <2>;

					bias-pull-down;

				};

			};

		};



	};

};

qcom/sm8150.dtsi

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@@ -1073,6 +1073,20 @@ 
		#freq-domain-cells = <2>;

	};



	qcom_clk_led: qcom_clk_led {

		compatible = "qcom,clk-led-pwm";

		qcom,label = "led_clk_gp2";

		clocks = <&gcc GCC_GP2_CLK>;

		clock-names = "core";

		assigned-clocks = <&gcc GCC_GP2_CLK>;

		assigned-clock-rates = <80000>;

		qcom,max_duty = <53>;

		pinctrl-names = "active", "sleep";

		pinctrl-0 = <&qcom_clk_led_gp2_active>;

		pinctrl-1 = <&qcom_clk_led_gp2_sleep>;

		status = "disabled";

	};



	spmi_bus: qcom,spmi@c440000 {

		compatible = "qcom,spmi-pmic-arb";

		reg = <0xc440000 0x1100>,