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Commit 11a6194b authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "soc: qcom: llcc: Add support for CPU TLB System Cache Id"

parents b186c507 3b821d84

drivers/soc/qcom/llcc-lahaina.c

+2 −1
Original line number Diff line number Diff line
@@ -60,7 +60,7 @@ static struct llcc_slice_config lahaina_data[] = { 
	SCT_ENTRY(LLCC_GPUHTW,   11, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0),

	SCT_ENTRY(LLCC_GPU,      12, 1024, 1, 0, 0xFFF, 0x0, 0, 0, 0, 1, 1, 0),

	SCT_ENTRY(LLCC_MMUHWT,   13, 1024, 1, 1, 0xFFF,  0x0, 0, 0, 0, 0, 0, 1),

	SCT_ENTRY(LLCC_DISP,     16, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0),

	SCT_ENTRY(LLCC_DISP,     16, 3072, 2, 1, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0),

	SCT_ENTRY(LLCC_MDMPNG,   21, 1024, 0, 1, 0xF,  0x0, 0, 0, 0, 0, 1, 0),

	SCT_ENTRY(LLCC_AUDHW,    22, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0),

	SCT_ENTRY(LLCC_CVP,      28, 512, 3, 1, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0),
@@ -69,6 +69,7 @@ static struct llcc_slice_config lahaina_data[] = { 
	SCT_ENTRY(LLCC_WRTCH,    31, 512, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 0, 1),

	SCT_ENTRY(LLCC_CVPFW,    17, 512, 1, 0, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0),

	SCT_ENTRY(LLCC_CPUSS1,   3, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0),

	SCT_ENTRY(LLCC_CPUHWT,   5, 512, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 0, 1),

};



static int lahaina_qcom_llcc_probe(struct platform_device *pdev)

include/linux/soc/qcom/llcc-qcom.h

+2 −1
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0 */

/*

 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.

 * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.

 *

 */
@@ -33,6 +33,7 @@ 
#define LLCC_WRTCH       31

#define LLCC_CVPFW       32

#define LLCC_CPUSS1      33

#define LLCC_CPUHWT      36



/**

 * llcc_slice_desc - Cache slice descriptor