soc: qcom: llcc: Add support for CPU TLB System Cache Id

Enable the CPU TLB System Cache Id by adding CPUHWT entry
to the Lahaina's LLCC SCT list and move the priority of
LCC_DISP to 2.

Change-Id: I0184d4f997961782d51ed98c18e19e3bbc67759a
Signed-off-by: Raghavendra Rao Ananta <rananta@codeaurora.org>