Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 0fe1fb06 authored by NITHEESH MUTHURAJ's avatar NITHEESH MUTHURAJ
Browse files

ARM: dts: msm: Add a new power level for supported devices 

Add speed bin node for efuse check and create speed
bins to include TURBO_L2 on supported devices.

Change-Id: I9ae248a599d53134b5e7b8a71ad109a34f1dfa0d
parent cab2b656

qcom/lahaina-gpu.dtsi

+3 −0
Original line number Diff line number Diff line
@@ -51,6 +51,9 @@ 


		qcom,gpu-qdss-stm = <0x161c0000 0x40000>; /* base addr, size */



		nvmem-cells = <&gpu_speed_bin>;

		nvmem-cell-names = "speed_bin";



		qcom,tzone-names = "gpuss-0-usr", "gpuss-1-usr";



		interconnects = <&gem_noc MASTER_GFX3D &mc_virt SLAVE_EBI1>;

qcom/lahaina-v2-gpu.dtsi

+313 −122
Original line number Diff line number Diff line 
&msm_gpu {

	qcom,chipid = <0x06060001>;



	qcom,initial-pwrlevel = <9>;

	/delete-property/qcom,initial-pwrlevel;

	/delete-node/qcom,gpu-pwrlevels;



	/* Power levels */

	qcom,gpu-pwrlevels {

	/* Power levels bins */

	qcom,gpu-pwrlevel-bins {

		compatible="qcom,gpu-pwrlevel-bins";

		#address-cells = <1>;

		#size-cells = <0>;



		compatible = "qcom,gpu-pwrlevels";

		qcom,gpu-pwrlevels-0 {

			#address-cells = <1>;

			#size-cells = <0>;

			qcom,speed-bin = <0>;

			qcom,initial-pwrlevel = <9>;



			qcom,gpu-pwrlevel@0 {

				reg = <0>;
@@ -169,5 +175,190 @@ 


				qcom,acd-level = <0x882f5ffd>;

			};



		};



		qcom,gpu-pwrlevels-1 {

			#address-cells = <1>;

			#size-cells = <0>;

			qcom,speed-bin = <1>;

			qcom,initial-pwrlevel = <10>;



			qcom,gpu-pwrlevel@0 {

				reg = <0>;

				qcom,gpu-freq = <900000000>;

				qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L2>;



				qcom,bus-freq-ddr7 = <11>;

				qcom,bus-min-ddr7 = <11>;

				qcom,bus-max-ddr7 = <11>;



				qcom,bus-freq-ddr8 = <11>;

				qcom,bus-min-ddr8 = <11>;

				qcom,bus-max-ddr8 = <11>;



				qcom,acd-level = <0x882a5ffd>;

			};



			qcom,gpu-pwrlevel@1 {

				reg = <1>;

				qcom,gpu-freq = <840000000>;

				qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;



				qcom,bus-freq-ddr7 = <11>;

				qcom,bus-min-ddr7 = <11>;

				qcom,bus-max-ddr7 = <11>;



				qcom,bus-freq-ddr8 = <11>;

				qcom,bus-min-ddr8 = <11>;

				qcom,bus-max-ddr8 = <11>;



				qcom,acd-level = <0x882a5ffd>;

			};



			qcom,gpu-pwrlevel@2 {

				reg = <2>;

				qcom,gpu-freq = <778000000>;

				qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;



				qcom,bus-freq-ddr7 = <11>;

				qcom,bus-min-ddr7 = <11>;

				qcom,bus-max-ddr7 = <11>;



				qcom,bus-freq-ddr8 = <11>;

				qcom,bus-min-ddr8 = <11>;

				qcom,bus-max-ddr8 = <11>;



				qcom,acd-level = <0xa82a5ffd>;

			};



			qcom,gpu-pwrlevel@3 {

				reg = <3>;

				qcom,gpu-freq = <738000000>;

				qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;



				qcom,bus-freq-ddr7 = <11>;

				qcom,bus-min-ddr7 = <11>;

				qcom,bus-max-ddr7 = <11>;



				qcom,bus-freq-ddr8 = <11>;

				qcom,bus-min-ddr8 = <11>;

				qcom,bus-max-ddr8 = <11>;



				qcom,acd-level = <0xa82a5ffd>;

			};



			qcom,gpu-pwrlevel@4 {

				reg = <4>;

				qcom,gpu-freq = <676000000>;

				qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;



				qcom,bus-freq-ddr7 = <11>;

				qcom,bus-min-ddr7 = <11>;

				qcom,bus-max-ddr7 = <11>;



				qcom,bus-freq-ddr8 = <10>;

				qcom,bus-min-ddr8 = <10>;

				qcom,bus-max-ddr8 = <11>;



				qcom,acd-level = <0x882b5ffd>;

			};



			qcom,gpu-pwrlevel@5 {

				reg = <5>;

				qcom,gpu-freq = <608000000>;

				qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;



				qcom,bus-freq-ddr7 = <8>;

				qcom,bus-min-ddr7 = <7>;

				qcom,bus-max-ddr7 = <11>;



				qcom,bus-freq-ddr8 = <7>;

				qcom,bus-min-ddr8 = <7>;

				qcom,bus-max-ddr8 = <11>;



				qcom,acd-level = <0xa82b5ffd>;

			};



			qcom,gpu-pwrlevel@6 {

				reg = <6>;

				qcom,gpu-freq = <540000000>;

				qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;



				qcom,bus-freq-ddr7 = <8>;

				qcom,bus-min-ddr7 = <7>;

				qcom,bus-max-ddr7 = <10>;



				qcom,bus-freq-ddr8 = <7>;

				qcom,bus-min-ddr8 = <7>;

				qcom,bus-max-ddr8 = <9>;



				qcom,acd-level = <0xa82c5ffd>;

			};



			qcom,gpu-pwrlevel@7 {

				reg = <7>;

				qcom,gpu-freq = <491000000>;

				qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L0>;



				qcom,bus-freq-ddr7 = <8>;

				qcom,bus-min-ddr7 = <6>;

				qcom,bus-max-ddr7 = <10>;



				qcom,bus-freq-ddr8 = <7>;

				qcom,bus-min-ddr8 = <5>;

				qcom,bus-max-ddr8 = <7>;



				qcom,acd-level = <0xa82c5ffd>;

			};



			qcom,gpu-pwrlevel@8 {

				reg = <8>;

				qcom,gpu-freq = <443000000>;

				qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;



				qcom,bus-freq-ddr7 = <8>;

				qcom,bus-min-ddr7 = <6>;

				qcom,bus-max-ddr7 = <10>;



				qcom,bus-freq-ddr8 = <7>;

				qcom,bus-min-ddr8 = <5>;

				qcom,bus-max-ddr8 = <7>;



				qcom,acd-level = <0xa82d5ffd>;

			};



			qcom,gpu-pwrlevel@9 {

				reg = <9>;

				qcom,gpu-freq = <379000000>;

				qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;



				qcom,bus-freq-ddr7 = <8>;

				qcom,bus-min-ddr7 = <6>;

				qcom,bus-max-ddr7 = <10>;



				qcom,bus-freq-ddr8 = <6>;

				qcom,bus-min-ddr8 = <5>;

				qcom,bus-max-ddr8 = <7>;



				qcom,acd-level = <0x882e5ffd>;

			};



			qcom,gpu-pwrlevel@10 {

				reg = <10>;

				qcom,gpu-freq = <315000000>;

				qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;



				qcom,bus-freq-ddr7 = <2>;

				qcom,bus-min-ddr7 = <2>;

				qcom,bus-max-ddr7 = <9>;



				qcom,bus-freq-ddr8 = <2>;

				qcom,bus-min-ddr8 = <2>;

				qcom,bus-max-ddr8 = <7>;



				qcom,acd-level = <0x882f5ffd>;

			};

		};

	};

};

qcom/lahaina.dtsi

+14 −0
Original line number Diff line number Diff line
@@ -5657,6 +5657,20 @@ 
		qcom,use-ap-power-save;

		status = "disabled";

	};



	qfprom: qfprom@784000 {

		compatible = "qcom,qfprom";

		reg = <0x784000 0x3000>;

		#address-cells = <1>;

		#size-cells = <1>;

		read-only;

		ranges;



		gpu_speed_bin: gpu_speed_bin@17b {

				reg = <0x17b 0x1>;

				bits = <5 3>;

		};

	};

};



#include "ipcc-test.dtsi"