Loading qcom/sdxlemur-1024mb.dtsi 0 → 100644 +9 −0 Original line number Diff line number Diff line #include "sdxlemur-512mb.dtsi" &mpss_adsp_mem { reg = <0x90800000 0x10000000>; }; &access_control_mem { reg = <0x8fd80000 0x80000>; }; qcom/sdxlemur-512mb.dtsi 0 → 100644 +53 −0 Original line number Diff line number Diff line &reserved_memory { mpss_adsp_mem: mpss_adsp_region@90800000 { no-map; reg = <0x90800000 0xF800000>; }; tz_mem: tz_mem_region@8ff00000 { no-map; reg = <0x8ff00000 0x600000>; }; cmd_db: reserved-memory@8fee0000 { compatible = "qcom,cmd-db"; no-map; reg = <0x8fee0000 0x20000>; }; smem_mem: smem_region@8fe20000 { no-map; reg = <0x8fe20000 0xc0000>; label = "smem_mem"; }; aop_mem: aop_regions@0x8fe00000 { no-map; reg = <0x8fe00000 0x20000>; }; access_control_mem: access_control_region@8fd80000 { no-map; reg = <0x8fd80000 0x40000>; }; hyp_mem: hyp_region@8fd00000 { no-map; reg = <0x8fd00000 0x80000>; }; secdata_mem: secdata_region@0x8fcfd000 { no-map; reg = <0x8fcfd000 0x1000>; }; ipa_fw_mem: ipa_fw_region@0x8fced000 { no-map; reg = <0x8fced000 0x10000>; }; mpss_dsm: mpss_dsm_region@8c400000 { no-map; reg = <0x8c400000 0x3200000>; }; }; qcom/sdxlemur-cdp.dts +1 −1 Original line number Diff line number Diff line Loading @@ -2,7 +2,7 @@ #include "sdxlemur.dtsi" #include "sdxlemur-cdp.dtsi" #include "sdxlemur-1024mb.dtsi" / { model = "Qualcomm Technologies, Inc. SDXLEMUR CDP"; compatible = "qcom,sdxlemur-cdp", Loading qcom/sdxlemur-mtp-cpe.dts +1 −0 Original line number Diff line number Diff line Loading @@ -2,6 +2,7 @@ #include "sdxlemur.dtsi" #include "sdxlemur-mtp-cpe.dtsi" #include "sdxlemur-1024mb.dtsi" / { model = "Qualcomm Technologies, Inc. SDXLEMUR MTP CPE"; Loading qcom/sdxlemur-mtp-mbb-ntn3-pcie.dts +1 −0 Original line number Diff line number Diff line Loading @@ -2,6 +2,7 @@ #include "sdxlemur.dtsi" #include "sdxlemur-mtp-mbb-ntn3-pcie.dtsi" #include "sdxlemur-1024mb.dtsi" / { model = "Qualcomm Technologies, Inc. SDXLEMUR MTP MBB NTN3 PCIE"; Loading Loading
qcom/sdxlemur-1024mb.dtsi 0 → 100644 +9 −0 Original line number Diff line number Diff line #include "sdxlemur-512mb.dtsi" &mpss_adsp_mem { reg = <0x90800000 0x10000000>; }; &access_control_mem { reg = <0x8fd80000 0x80000>; };
qcom/sdxlemur-512mb.dtsi 0 → 100644 +53 −0 Original line number Diff line number Diff line &reserved_memory { mpss_adsp_mem: mpss_adsp_region@90800000 { no-map; reg = <0x90800000 0xF800000>; }; tz_mem: tz_mem_region@8ff00000 { no-map; reg = <0x8ff00000 0x600000>; }; cmd_db: reserved-memory@8fee0000 { compatible = "qcom,cmd-db"; no-map; reg = <0x8fee0000 0x20000>; }; smem_mem: smem_region@8fe20000 { no-map; reg = <0x8fe20000 0xc0000>; label = "smem_mem"; }; aop_mem: aop_regions@0x8fe00000 { no-map; reg = <0x8fe00000 0x20000>; }; access_control_mem: access_control_region@8fd80000 { no-map; reg = <0x8fd80000 0x40000>; }; hyp_mem: hyp_region@8fd00000 { no-map; reg = <0x8fd00000 0x80000>; }; secdata_mem: secdata_region@0x8fcfd000 { no-map; reg = <0x8fcfd000 0x1000>; }; ipa_fw_mem: ipa_fw_region@0x8fced000 { no-map; reg = <0x8fced000 0x10000>; }; mpss_dsm: mpss_dsm_region@8c400000 { no-map; reg = <0x8c400000 0x3200000>; }; };
qcom/sdxlemur-cdp.dts +1 −1 Original line number Diff line number Diff line Loading @@ -2,7 +2,7 @@ #include "sdxlemur.dtsi" #include "sdxlemur-cdp.dtsi" #include "sdxlemur-1024mb.dtsi" / { model = "Qualcomm Technologies, Inc. SDXLEMUR CDP"; compatible = "qcom,sdxlemur-cdp", Loading
qcom/sdxlemur-mtp-cpe.dts +1 −0 Original line number Diff line number Diff line Loading @@ -2,6 +2,7 @@ #include "sdxlemur.dtsi" #include "sdxlemur-mtp-cpe.dtsi" #include "sdxlemur-1024mb.dtsi" / { model = "Qualcomm Technologies, Inc. SDXLEMUR MTP CPE"; Loading
qcom/sdxlemur-mtp-mbb-ntn3-pcie.dts +1 −0 Original line number Diff line number Diff line Loading @@ -2,6 +2,7 @@ #include "sdxlemur.dtsi" #include "sdxlemur-mtp-mbb-ntn3-pcie.dtsi" #include "sdxlemur-1024mb.dtsi" / { model = "Qualcomm Technologies, Inc. SDXLEMUR MTP MBB NTN3 PCIE"; Loading