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Commit 0ecc471a authored by Hanjun Guo's avatar Hanjun Guo Committed by Catalin Marinas
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arm64: kpti: Whitelist HiSilicon Taishan v110 CPUs 



HiSilicon Taishan v110 CPUs didn't implement CSV3 field of the
ID_AA64PFR0_EL1 and are not susceptible to Meltdown, so whitelist
the MIDR in kpti_safe_list[] table.

Signed-off-by: default avatarHanjun Guo <hanjun.guo@linaro.org>
Reviewed-by: default avatarJohn Garry <john.garry@huawei.com>
Reviewed-by: default avatarZhangshaokun <zhangshaokun@hisilicon.com>
Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent efd00c72

arch/arm64/kernel/cpufeature.c

+1 −0
Original line number Original line Diff line number Diff line
@@ -963,6 +963,7 @@ static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry, 
		MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),

		MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),

		MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),

		MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),

		MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),

		MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),

		MIDR_ALL_VERSIONS(MIDR_HISI_TSV110),

		{ /* sentinel */ }

		{ /* sentinel */ }

	};

	};

	char const *str = "command line option";

	char const *str = "command line option";