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Commit efd00c72 authored by Hanjun Guo's avatar Hanjun Guo Committed by Catalin Marinas
Browse files

arm64: Add MIDR encoding for HiSilicon Taishan CPUs 



Adding the MIDR encodings for HiSilicon Taishan v110 CPUs,
which is used in Kunpeng ARM64 server SoCs. TSV110 is the
abbreviation of Taishan v110.

Signed-off-by: default avatarHanjun Guo <hanjun.guo@linaro.org>
Reviewed-by: default avatarJohn Garry <john.garry@huawei.com>
Reviewed-by: default avatarZhangshaokun <zhangshaokun@hisilicon.com>
Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent c82fd1e6

arch/arm64/include/asm/cputype.h

+4 −0
Original line number Diff line number Diff line
@@ -77,6 +77,7 @@ 
#define ARM_CPU_IMP_QCOM		0x51

#define ARM_CPU_IMP_NVIDIA		0x4E

#define ARM_CPU_IMP_FUJITSU		0x46

#define ARM_CPU_IMP_HISI		0x48



#define ARM_CPU_PART_AEM_V8		0xD0F

#define ARM_CPU_PART_FOUNDATION		0xD00
@@ -107,6 +108,8 @@ 


#define FUJITSU_CPU_PART_A64FX		0x001



#define HISI_CPU_PART_TSV110		0xD01



#define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)

#define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)

#define MIDR_CORTEX_A72 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72)
@@ -126,6 +129,7 @@ 
#define MIDR_NVIDIA_DENVER MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_DENVER)

#define MIDR_NVIDIA_CARMEL MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_CARMEL)

#define MIDR_FUJITSU_A64FX MIDR_CPU_MODEL(ARM_CPU_IMP_FUJITSU, FUJITSU_CPU_PART_A64FX)

#define MIDR_HISI_TSV110 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_TSV110)



/* Fujitsu Erratum 010001 affects A64FX 1.0 and 1.1, (v0r0 and v1r0) */

#define MIDR_FUJITSU_ERRATUM_010001		MIDR_FUJITSU_A64FX