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Commit 0e44d48c authored by Mohammed Shafi Shajakhan's avatar Mohammed Shafi Shajakhan Committed by John W. Linville
Browse files

ath9k_hw: make sure PAPRD training is properly done 



checking the status of PAPRD_AGC2_POWER(Log(ADC_power) measured after
last gain-change in dB) field suggests whether the PAPRD is completely/properly
done. This is an additional check apart from polling for PAPRD done bit being set.
        Susinder suggests that the ideal power range value should be
0xf0 to 0xfe. With AR9382 we do have the values in this range. to have a
common check for all platforms we take agc2_power should be atleast greater
than 0xe0

Cc: susinder@qca.qualcomm.com
Cc: senthilb@qca.qualcomm.com
Cc: kmuthusa@qca.qualcomm.com
Signed-off-by: default avatarMohammed Shafi Shajakhan <mohammed@qca.qualcomm.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent 81dc6760

drivers/net/wireless/ath/ath9k/ar9003_paprd.c

+20 −1
Original line number Diff line number Diff line
@@ -785,7 +785,26 @@ EXPORT_SYMBOL(ar9003_paprd_init_table); 


bool ar9003_paprd_is_done(struct ath_hw *ah)

{

	return !!REG_READ_FIELD(ah, AR_PHY_PAPRD_TRAINER_STAT1,

	int paprd_done, agc2_pwr;

	paprd_done = REG_READ_FIELD(ah, AR_PHY_PAPRD_TRAINER_STAT1,

				AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE);



	if (paprd_done == 0x1) {

		agc2_pwr = REG_READ_FIELD(ah, AR_PHY_PAPRD_TRAINER_STAT1,

				AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_AGC2_PWR);



		ath_dbg(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,

			"AGC2_PWR = 0x%x training done = 0x%x\n",

			agc2_pwr, paprd_done);

	/*

	 * agc2_pwr range should not be less than 'IDEAL_AGC2_PWR_CHANGE'

	 * when the training is completely done, otherwise retraining is

	 * done to make sure the value is in ideal range

	 */

		if (agc2_pwr <= PAPRD_IDEAL_AGC2_PWR_RANGE)

			paprd_done = 0;

	}



	return !!paprd_done;

}

EXPORT_SYMBOL(ar9003_paprd_is_done);

drivers/net/wireless/ath/ath9k/hw.h

+3 −2
Original line number Diff line number Diff line
@@ -159,6 +159,7 @@ 


#define PAPRD_GAIN_TABLE_ENTRIES	32

#define PAPRD_TABLE_SZ			24

#define PAPRD_IDEAL_AGC2_PWR_RANGE	0xe0



enum ath_hw_txq_subtype {

	ATH_TXQ_AC_BE = 0,