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Commit 0a33b6c1 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "dt-bindings: pinctrl: qcom-pmic-gpio: add PMR735A and PMR735B bindings"

parents 8bef2378 41580198

bindings/pinctrl/qcom,pmic-gpio.txt

+4 −0
Original line number Diff line number Diff line
@@ -27,6 +27,8 @@ PMIC's from Qualcomm. 
		    "qcom,pm8350b-gpio"

		    "qcom,pm8350c-gpio"

		    "qcom,pmk8350-gpio"

		    "qcom,pmr735a-gpio"

		    "qcom,pmr735b-gpio"



		    And must contain either "qcom,spmi-gpio" or "qcom,ssbi-gpio"

		    if the device is on an spmi bus or an ssbi bus respectively
@@ -108,6 +110,8 @@ to specify in a pin configuration subnode: 
		    gpio1-gpio8 for pm8350b

		    gpio1-gpio9 for pm8350c

		    gpio1-gpio4 for pmk8350

		    gpio1-gpio4 for pmr735a

		    gpio1-gpio4 for pmr735b



- function:

	Usage: required

qcom/lahaina.dtsi

+19 −0
Original line number Diff line number Diff line
@@ -1181,6 +1181,25 @@ 
				  <CONTROL_TCS 0>;

	};



	spmi_bus: qcom,spmi@c440000 {

		compatible = "qcom,spmi-pmic-arb";

		reg = <0xc440000 0x1100>,

		      <0xc600000 0x2000000>,

		      <0xe600000 0x100000>,

		      <0xe700000 0xa0000>,

		      <0xc40a000 0x26000>;

		reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";

		interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "periph_irq";

		interrupt-controller;

		#interrupt-cells = <4>;

		#address-cells = <2>;

		#size-cells = <0>;

		cell-index = <0>;

		qcom,channel = <0>;

		qcom,ee = <0>;

	};



	qcom,msm-cdsp-loader {

		compatible = "qcom,cdsp-loader";

		qcom,proc-img-to-load = "cdsp";