Loading drivers/gpu/msm/adreno_a6xx.c +4 −0 Original line number Diff line number Diff line Loading @@ -49,6 +49,7 @@ static u32 a6xx_pwrup_reglist[] = { A6XX_SP_NC_MODE_CNTL, A6XX_PC_DBG_ECO_CNTL, A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE, A6XX_UCHE_GBIF_GX_CONFIG, }; /* IFPC only static powerup restore list */ Loading Loading @@ -372,6 +373,9 @@ static void a6xx_hwcg_set(struct adreno_device *adreno_dev, bool on) kgsl_regwrite(device, a6xx_core->hwcg[i].offset, on ? a6xx_core->hwcg[i].value : 0); /* GBIF L2 CGC control is not part of the UCHE */ kgsl_regrmw(device, A6XX_UCHE_GBIF_GX_CONFIG, 0x70000, on ? 2 : 0); /* * Enable SP clock after programming HWCG registers. * A612 and A610 GPU is not having the GX power domain. Loading Loading
drivers/gpu/msm/adreno_a6xx.c +4 −0 Original line number Diff line number Diff line Loading @@ -49,6 +49,7 @@ static u32 a6xx_pwrup_reglist[] = { A6XX_SP_NC_MODE_CNTL, A6XX_PC_DBG_ECO_CNTL, A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE, A6XX_UCHE_GBIF_GX_CONFIG, }; /* IFPC only static powerup restore list */ Loading Loading @@ -372,6 +373,9 @@ static void a6xx_hwcg_set(struct adreno_device *adreno_dev, bool on) kgsl_regwrite(device, a6xx_core->hwcg[i].offset, on ? a6xx_core->hwcg[i].value : 0); /* GBIF L2 CGC control is not part of the UCHE */ kgsl_regrmw(device, A6XX_UCHE_GBIF_GX_CONFIG, 0x70000, on ? 2 : 0); /* * Enable SP clock after programming HWCG registers. * A612 and A610 GPU is not having the GX power domain. Loading
